Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 754-2008, w...Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 754-2008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are advantageous because there are no carry-propagate chains. The proposed signed-digit adder reduces the critical path delay by parallelizing the correction stage inherent to decimal addition. For performance evaluation, we synthesize and compare multiple unsigned and signed-digit multi-operand decimal adder architectures on 0.18μm CMOS VLSI technology. Synthesis results for 2, 4, 8, and 16 operands with 8 decimal digits provide critical data in determining each adder's performance and scalability.展开更多
Various designed circuits for multiple-valued all-optical arithmetic are demonstrated. The terahertz-optical-asymmetric-demultiplexer (TOAD) switch is used as the basic structure unit in the proposed circuits due to i...Various designed circuits for multiple-valued all-optical arithmetic are demonstrated. The terahertz-optical-asymmetric-demultiplexer (TOAD) switch is used as the basic structure unit in the proposed circuits due to its compact size, thermal stability, and low power operation. The designs of trinary and quaternary signed-digit numbers based adders are presented using different polarized states of light. These proposed polarization-encoded based adders use much less switches and their speeds are higher than the intensity-encoded counterparts. Further, it will be shown that one of the proposed trinary signed-digit adders is twice as fast as a recently reported modified signed-digit adder.展开更多
The division operation is not frequent relatively in traditional applications, but it is increasingly indispensable and important in many modern applications. In this paper, the implementation of modified signed-digit...The division operation is not frequent relatively in traditional applications, but it is increasingly indispensable and important in many modern applications. In this paper, the implementation of modified signed-digit (MSD) floating-point division using Newton-Raphson method on the system of ternary optical computer (TOC) is studied. Since the addition of MSD floating-point is carry-free and the digit width of the system of TOC is large, it is easy to deal with the enough wide data and transform the division operation into multiplication and addition operations. And using data scan and truncation the problem of digits expansion is effectively solved in the range of error limit. The division gets the good results and the efficiency is high. The instance of MSD floating-point division shows that the method is feasible.展开更多
Recently, security in embedded system arises attentions because of modern electronic devices need cau- tiously either exchange or communicate with the sensitive data. Although security is classical research topic in...Recently, security in embedded system arises attentions because of modern electronic devices need cau- tiously either exchange or communicate with the sensitive data. Although security is classical research topic in world- wide communication, the researchers still face the problems of how to deal with these resource constraint devices and en- hance the features of assurance and certification. Therefore, some computations of cryptographic algorithms are built on hardware platforms, such as field program gate arrays (FPGAs). The commonly used cryptographic algorithms for digital signature algorithm (DSA) are rivest-shamir-adleman (RSA) and elliptic curve cryptosystems (ECC) which based on the presumed difficulty of factoring large integers and the algebraic structure of elliptic curves over finite fields. Usu- ally, RSA is computed over GF(p), and ECC is computed over GF(p) or GF(2P). Moreover, embedded applications need advance encryption standard (AES) algorithms to pro- cess encryption and decryption procedures. In order to reuse the hardware resources and meet the trade-off between area and performance, we proposed a new triple functional arith- metic unit for computing high radix RSA and ECC operations over GF(p) and GF(2P), which also can be extended to support AES operations. A new high radix signed digital (SD) adder has been proposed to eliminate the carry propagations over GF(p). The proposed unified design took up 28.7% less hardware resources than implementing RSA, ECC, and AES individually, and the experimental results show that our proposed architecture can achieve 141.8 MHz using approxi- mately 5.5k CLBs on Virtex-5 FPGA.展开更多
文摘Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 754-2008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are advantageous because there are no carry-propagate chains. The proposed signed-digit adder reduces the critical path delay by parallelizing the correction stage inherent to decimal addition. For performance evaluation, we synthesize and compare multiple unsigned and signed-digit multi-operand decimal adder architectures on 0.18μm CMOS VLSI technology. Synthesis results for 2, 4, 8, and 16 operands with 8 decimal digits provide critical data in determining each adder's performance and scalability.
文摘Various designed circuits for multiple-valued all-optical arithmetic are demonstrated. The terahertz-optical-asymmetric-demultiplexer (TOAD) switch is used as the basic structure unit in the proposed circuits due to its compact size, thermal stability, and low power operation. The designs of trinary and quaternary signed-digit numbers based adders are presented using different polarized states of light. These proposed polarization-encoded based adders use much less switches and their speeds are higher than the intensity-encoded counterparts. Further, it will be shown that one of the proposed trinary signed-digit adders is twice as fast as a recently reported modified signed-digit adder.
基金Project supported by the Shanghai Leading Academic Discipline Project(Grant No.J50103)the National Natural Science Foundation of China(Grant No.61073049)
文摘The division operation is not frequent relatively in traditional applications, but it is increasingly indispensable and important in many modern applications. In this paper, the implementation of modified signed-digit (MSD) floating-point division using Newton-Raphson method on the system of ternary optical computer (TOC) is studied. Since the addition of MSD floating-point is carry-free and the digit width of the system of TOC is large, it is easy to deal with the enough wide data and transform the division operation into multiplication and addition operations. And using data scan and truncation the problem of digits expansion is effectively solved in the range of error limit. The division gets the good results and the efficiency is high. The instance of MSD floating-point division shows that the method is feasible.
基金This work was supported by National Natural Science Foundation of China (Grant No. 61173036) and the Fundamental Research Funds for Chinese Central Universities.
文摘Recently, security in embedded system arises attentions because of modern electronic devices need cau- tiously either exchange or communicate with the sensitive data. Although security is classical research topic in world- wide communication, the researchers still face the problems of how to deal with these resource constraint devices and en- hance the features of assurance and certification. Therefore, some computations of cryptographic algorithms are built on hardware platforms, such as field program gate arrays (FPGAs). The commonly used cryptographic algorithms for digital signature algorithm (DSA) are rivest-shamir-adleman (RSA) and elliptic curve cryptosystems (ECC) which based on the presumed difficulty of factoring large integers and the algebraic structure of elliptic curves over finite fields. Usu- ally, RSA is computed over GF(p), and ECC is computed over GF(p) or GF(2P). Moreover, embedded applications need advance encryption standard (AES) algorithms to pro- cess encryption and decryption procedures. In order to reuse the hardware resources and meet the trade-off between area and performance, we proposed a new triple functional arith- metic unit for computing high radix RSA and ECC operations over GF(p) and GF(2P), which also can be extended to support AES operations. A new high radix signed digital (SD) adder has been proposed to eliminate the carry propagations over GF(p). The proposed unified design took up 28.7% less hardware resources than implementing RSA, ECC, and AES individually, and the experimental results show that our proposed architecture can achieve 141.8 MHz using approxi- mately 5.5k CLBs on Virtex-5 FPGA.