CNTFET Based Grounded Active Inductor for Broadband Applications

A new carbon nanotube field effect transistor(CNTFET)based grounded active inductor(GAI)circuit is presented in this work.The suggested GAI offers a tunable inductance with a very wide inductive bandwidth,high quality factor(QF)and low power dissipation.The tunability of the realized circuit is achieved through CNTFET based varactor.The proposed topology shows inductive behavior in the frequency range of 0.1–101 GHz and achieves to a maximum QF of 9125.The GAI operates at 0.7 V with 0.337 mW of power consumption.To demonstrate the performance of GAI,a broadband low noise amplifier(LNA)circuit is designed by utilizing the GAI based input matching-network.The realized LNA provides high frequency bandwidth(17.5–57 GHz),low noise figure(<3 dB)and occupies less space due to absence of any spiral inductor.Moreover,it exhibits a flat forward gain of 15.9 than±0.9 dB,a reverse isolation less than−63 dB and input return loss less−10 dB over the entire frequency bandwidth.The proposed CNTFET based GAI and LNA circuits are designed and verified by using HSPICE simulations with Stanford CNTFET model at 16 nm technology node.

Effect of lateral structure parameters of SiGe HBTs on synthesized active inductors

The effect of lateral structure parameters of transistors including emitter width, emitter length, and emitter stripe number on the performance parameters of the active inductor （AI）, such as the effective inductance Ls, quality factor Q, and self-resonant frequency too is analyzed based on 0.35%tm SiGe BiCMOS process. The simulation results show that for AI operated under fixed current density Jc, the HBT lateral structure parameters have significant effect on Ls but little influence on Q and 090, and the larger Ls can be realized by the narrow, short emitter stripe and few emitter stripes of SiGe HBTs. On the other hand, for AI with fixed HBT size, smaller Jc is beneficial for AI to obtain larger Ls, but with a cost of smaller Q and 090. In addition, under the fixed collector current Ic, the larger the size of HBT is, the larger Ls becomes, but the smaller Q and ab become. The obtained results provide a reference for selecting geometry of transistors and operational condition in the design of active inductors.

A compact and reconfigurable low noise amplifier employing combinational active inductors and composite resistors feedback techniques

A compact and reconfigurable low noise amplifier(LNA)is proposed by combining an input transistor,composite transistors with Darlington configuration as the amplification and output transistor,T-type structure composite resistors instead of a simplex structure resistor,a shunt inductor feedback realized by a tunable active inductor(AI),a shunt inductor peaking technique realized by another tunable AI.The division and collaboration among different resistances in the T-type structure composite resistor realize simultaneously input impedance matching,output impedance matching and good noise performance;the shunt feedback and peaking technique using two tunable AIs not only extend frequency bandwidth and improve gain flatness,but also make the gain and frequency band can be tuned simultaneously by the external bias of tunable AIs;the Darlington configuration of composite transistors provides high gain;furthermore,the adoption of the small size AIs instead of large size passive spiral inductor,and the use of composite resistors make the LNA have a small size.The LNA is fabricated and verified by GaAs/InGaP hetero-junction bipolar transistor(HBT)process.The results show that at the frequency of 7 GHz,the gain S_(21)is maximum and up to 19 dB;the S_(21)can be tuned from 17 dB to 19 dB by tuning external bias of tunable AIs,that is,the tunable amount of S_(21)is 2 dB,and similarly at 8 GHz;the tunable range of 3 dB bandwidth is 1 GHz.In addition,the gain S_(21)flatness is better than 0.4 dB under frequency from 3.1 GHz to 10.6 GHz;the size of the LNA only has 760μm×1260μm(including PADs).Therefore,the proposed strategies in the paper provide a new solution to the design of small size and reconfigurable ultra-wideband(UWB)LNA and can be used further to adjust the variations of gain and bandwidth of radio frequency integrated circuits(RFICs)due to package,parasitic and the variation of fabrication process and temperature.

Active inductor shunt peaking in high-speed VCSEL driver design

An all-transistor active-inductor shunt-peaking structure has been used in a prototype of 8 Gbps high- speed VCSEL driver which is designed for the optical link in ATLAS liquid Argon calorimeter upgrade. The VCSEL driver is fabricated in a commercial 0.25 p^m Silicon-on-Sapphire （SOS） CMOS process for radiation tolerant purpose. The all-transistor active-inductor shunt-peaking is used to overcome the bandwidth limitation from the CMOS pro- cess. The peaking structure has the same peaking effect as the passive one, but takes a small area, does not need linear resistors and can overcome the process variation by adjust the peaking strength via an external control. The design has been taped out, and the prototype has been proven by the preliminary electrical test results and bit error ratio test results. The driver achieves 8 Gbps data rate as simulated with the peaking. We present the all-transistor active-inductor shunt-peaking structure, simulation and test results in this paper.

Design and Implementation of an Optoelectronic Integrated Receiver in Standard CMOS Process

A wideband monolithic optoelectronic integrated receiver with a high-speed photo-detector,completely compatible with standard CMOS processes,is designed and implemented in 0.6μm standard CMOS technology.The experimental results demonstrate that its performance approaches applicable requirements,where the photo-detector achieves a -3dB frequency of 1.11GHz,and the receiver achieves a 3dB bandwidth of 733MHz and a sensitivity of -9dBm for λ=850nm at BER=10-12.

A Q-Enhanced CMOS RF Filter for Multi-Band Wireless Communications

An RF bandpass filter with a Q-enhancement active inductor is presented. The design technique for a tunable Q-enhancement CMOS active inductor operating in the wide RF-band is described. Moreover,issues related to noise and stability of the active inductor are explained. The filter was fabricated in 0.18μm CMOS technolo- gy,and the circuit occupied an active area of only 150μm ×200μm. Measurement results show that the filter centered at 2. 44GHz with about 60MHz bandwidth （3dB） is tunable in center frequency from about 2.07 to 2. 44GHz. The ldB compression point is - 15dBm while consuming 10. 8mW of DC power,and a maximum quality factor of 103 is attained at the center frequency of 2.07GHz.

5Gb/s 0.25μm CMOS Limiting Amplifier

A limiting amplifier (LA) IC implemented in TSMC standard 0.25μm CMOS technology is described.Active inductor loads and direct-coupled technology are employed to increase the gain,broaden the bandwidth,reduce the power dissipation,and keep a tolerable noise performance.Under a 3.3V supply voltage,the LA core achieves a gain of 50-dB with a power consumption below 40mW.The measured input sensitivity of the amplifier is better than 5m V _ pp .It can operate at bit rates up to 7Gb/s with an rms jitter of 0.03 UI or less.The chip area is only 0.70mm×0.70mm.According to the measurement results,this IC is expected to work at the standard bit rate levels of 2.5,3.125,and 5Gb/s.

A Low Noise,1.25Gb/s Front-End Amplifier for Optical Receivers

This paper presents a low noise, 1.25Gb/s and 124dBΩ front-end amplifier that is designed and fabricated in 0.25μm CMOS technology for optical communication applications. Active inductor shunt peaking technology and noise optimization are used in the design of a trans-impedance amplifier,which overcomes the problem of inadequate bandwidth caused by the large parasitical capacitor of the CMOS photodiode. Experimental results indicate that with a parasitical capacitance of 2pF,this circuit works at 1.25Gb/s. A clear eye diagram is obtained with an input optical signal of - 17dBm. With a power supply of 3.3V, the front-end amplifier consumes 122mW and provides a 660mV differential output.

LOW-POWER LVDS I/O INTERFACE FOR ABOVE 2GB/S-PER-PIN OPERATION

Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.

High-Gm Differential Regulated Cascode Transimpedance Amplifier

A differential cross-coupled regulated cascode(RGC)transimpedance amplifier(TIA)is proposed. The theory of multi-stage common-source(CS) configuration as an auxiliary amplifier to enhance the bandwidth and output impedance of RGC topology is analyzed. Additionally, negative Miller capacitance and shunt active inductor compensation are exploited to further expand the bandwidth. The proposed RGC TIA is simulated based on UMC 0.18 μm standard CMOS process. The simulation results demonstrate that the proposed TIA has a high transimpedance of 60.5 d B?, and a-3 d B bandwidth of 5.4 GHz is achieved for 0.5 p F input capacitance. The average equivalent input noise current spectral density is about 20 p A/Hz^(1/2) in the interested frequency, and the TIA consumes 20 m W DC power under 1.8 V supply voltage. The voltage swing is 460 m V pp, and the saturation input current is 500 μA.

A 5 Gb/s transceiver in 0.13μm CMOS for PCIE2.0

This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC＇s 0.13μm CMOS technology.The active area of the transceiver is 0.016 mm^2 and it consumes a total of 150 mW power at a 1.2 V supply voltage.The transmitter uses two stage pre-emphasis circuits with active inductors,reducing inter-symbol interference and extended bandwidth;the receiver uses a time-domain adaptive equalizer,the circuit uses an inductive peaking technique and extends the bandwidth,and the use of active inductors reduces the circuit area and power consumption effectively.The measurement results show that this circuit could stably transmit the signal at the data rate of 5 Gbps,the output signal swing of the transmitter is 350 mV with jitter of 14 ps,the eye opening of the receiver is 135 mV and the eye width is 0.56 UI.The circuit performance sufficiently meets the requirements of the PCI-Express 2.0 protocol.

Performanceanalysisofalowpowerlownoisetunablebandpassfilterformultiband RF front end

This paper presents a low power tunable active inductor and RF band pass filter suitable for multiband RF front end circuits. The active inductor circuit uses the PMOS cascode structure as the negative transconductor of a gyrator to reduce the noise voltage. Also, this structure provides possible negative resistance to reduce the inductor loss with wide inductive bandwidth and high resonance frequency. The RF band pass filter is realized using the proposed active inductor with suitable input and output buffer stages. The tuning of the center frequency for multiband operation is achieved through the controllable current source. The designed active inductor and RF band pass filter are simulated in 180 nm and 45 nm CMOS process using the Synopsys HSPICE simulation tool and their performances are compared. The parameters, such as resonance frequency, tuning capability, noise and power dissipation, are analyzed for these CMOS technologies and discussed. The design of a third order band pass filter using an active inductor is also presented.