采用Cascode拓扑和RC反馈网络的高Q差分有源电感

针对传统全差分有源电感在高频下品质因子Q较低的问题,联合使用Cascode拓扑和RC反馈网络对其进行优化。组合电路引入的双重负阻有效抵消了有源电感的寄生电阻,进而有效提高了高频下的Q值。基于Jazz 0.35μm SiGe BiCMOS工艺,利用射频仿真软件ADS完成电路设计与仿真。仿真结果表明,在联合采用了Cascode拓扑和RC反馈网络后,在频率大于1GHz时,有源电感的Q值明显提高;在1.3~3GHz频率范围内,Q值均大于20;在2.1GHz时,Q值达到最大值4 416,电感值变化范围为6.9~12nH。

Cascode混沌电路负阻模型与电路设计

针对 Cascode 结构振荡器进行研究,通过理论推导和分析,给出两级负阻提升的通用模型,该模型可以被广泛应用于混沌电路设计中,实际电路设计时可以用合适的负阻电路单元替代两级结构中的下级部分,实现电路负阻的提升。仿真设计结果表明,基于该模型设计的混沌电路的混沌振荡基频 f0为 4.2 GHz,f0/fT值达到 0.46,较经典单级电路有较大提升。

Cascode GaN高电子迁移率晶体管高频驱动电路及损耗分析

为了减小氮化镓驱动电路高频工作时的损耗,针对共栅共源氮化镓高电子迁移率晶体管(Cascode GaN HEMT)提出一种高频谐振驱动电路,采用储能元件替代传统驱动电路中的耗能元件,电感电流为GaN器件栅极电容充/放电,有源密勒钳位电路抑制桥臂串扰。该文重点研究高频谐振驱动电路的工作模态,对电路损耗进行详细分析,给出电感取值的选取原则,并利用PSIM软件对电路进行仿真。最终搭建实验平台对电路的性能进行测试。结果表明,电感为电容充/放电提供低阻抗通路,能有效减小GaN器件驱动电路的电压振荡,明显降低驱动电路的损耗。仿真和实验同时证明了所提出的电路具有较好的性能。

Cascode结构微波混沌振荡器的设计

提出了一种应用于宽带混沌信号发生器的Cascode结构微波混沌振荡器。利用微波晶体管BFG520对混沌振荡电路进行了设计和验证,通过在振荡电路与输出端口之间增加射极跟随器实现输出隔离并降低负载牵引的影响。基于晶体管Gummel-Poon模型对电路进行了PSpice仿真,结果证明新结构在很宽的参数变化范围内具有混沌特性。数值计算和实验测试结果表明:相比经典Colpitts混沌振荡器,新结构的李亚谱诺夫指数的维度提升了20%,达到2.5;测试频谱的基本频率提升了33%,达到1.41GHz。

补偿网络对Cascode结构放大器线性度的改善

宽带功率放大器是现代多频段无线通信系统中的关键器件.Cascode结构由于其良好的带宽特性以及输出阻抗特性,被广泛应用在宽带功率放大器的设计当中.带宽和线性是宽带功率放大器的重要指标.通常用RLC补偿网络可以增加Cascode结构功率放大器的带宽.本文提出通过选择合适的RLC补偿网络电路参数,使得晶体管处于良好的工作状态,可以实现在增加Cascode放大器带宽的同时,改善其线性度.从电路原理上分析了——补偿网络改善功率放大器非线性的原因,并利用Volterra级数方法计算了三阶交调截止点(IP3),证实了IP3可以改善3dB±.采用2μm InGaP/GaAs HBT半导体工艺流片后,测试结果表明,其3dB工作宽带扩展了1GHz(带宽从1.5GHz扩展到2.5GHz),IP3改善了3dB,与计算结果非常一致.

基于Multisim的Cascode电路仿真分析

通过对Cascode电路的理论计算和用Multisim软件仿真,找出了Cascode电路中的优点和缺点,同时提出了用稳压二级管对电路进行改进,提高了Cascode电路的放大倍数、带负载的能力并且扩大了电路的带宽.设计采用先进的仿真软件Multi-sim对Cascode电路进行仿真,仿真研究与理论分析一致,为提高电路带宽提供了一个参考依据.

基于Cascode级间匹配的多频段LNA设计

提出了一种Cascode级间匹配电路,能够优化Cascode放大器的噪声系数、增益及高频稳定性。应用该电路,设计了一款多频段射频低噪声放大器(LNA)。采用0.25μm GaAs工艺进行实现,输入、输出阻抗匹配网络采用片外元件。测试结果表明,通过重配置片外元件的参数,该LNA可工作于0.7~1.1 GHz、1.6~2.1 GHz、2.3~2.8 GHz这三个频段,增益分别为25±2 dB、19.5±0.5 dB和18±1 dB,噪声系数分别低于0.6 dB、0.7 dB和0.9 dB,OIP3均大于30 dBm。该LNA对于GSM/WCDMA/LTE通信基站以及L/S频段接收机等设备具有一定的应用价值。

1.8VCascode电流基准源设计与仿真

针对传统基准电流源因沟道长度调制效应导致的支路电流不一致的问题,本文从电路分析原理出发,设计了一个Cascode结构的高阻抗电流基准源,详细分析了基准电路内部存在的反馈方式,Cascode电路以及自启动电路的工作原理,对支路电流进行了定性分析。基于Cadence Spectre仿真工具,完成了电路的设计与仿真、版图的绘制。通过仿真,在1.8V的电源电压、TSMC0.18μm CMOS的工艺下,电流基准源在达到正常工作状态后两支路能稳定输出10μA的电流且与电源电压无关,并提高了电路的输出阻抗;在-20℃~120℃下,温漂系数为133ppm/℃;电路功耗仅为58.33μW。符合设计目标。

A 58-dBΩ20-Gb/s inverter-based cascode transimpedance amplifier for optical communications

This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process.Multiple bandwidth enhancement techniques,including input bonding wire,input series on-chip inductive peak-ing and negative capacitance compensation,are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device,achieving an overall bandwidth enhancement ratio of 8.5.The electrical measure-ment shows TIA achieves 58 dBΩup to 12.7 GHz with a 180-fF off-chip photodetector.The optical measurement demonstrates a clear open eye of 20 Gb/s.The TIA dissipates 4 mW from a 1.2-V supply voltage.

High-Gm Differential Regulated Cascode Transimpedance Amplifier

A differential cross-coupled regulated cascode(RGC)transimpedance amplifier(TIA)is proposed. The theory of multi-stage common-source(CS) configuration as an auxiliary amplifier to enhance the bandwidth and output impedance of RGC topology is analyzed. Additionally, negative Miller capacitance and shunt active inductor compensation are exploited to further expand the bandwidth. The proposed RGC TIA is simulated based on UMC 0.18 μm standard CMOS process. The simulation results demonstrate that the proposed TIA has a high transimpedance of 60.5 d B?, and a-3 d B bandwidth of 5.4 GHz is achieved for 0.5 p F input capacitance. The average equivalent input noise current spectral density is about 20 p A/Hz^(1/2) in the interested frequency, and the TIA consumes 20 m W DC power under 1.8 V supply voltage. The voltage swing is 460 m V pp, and the saturation input current is 500 μA.

Experimental Evaluation of Medium-Voltage Cascode Gallium Nitride(GaN)Devices for Bidirectional DC-DC Converters

Wide bandgap(WBG)semiconductors,such as silicon carbide(SiC)and gallium nitride(GaN),exhibit superior physical properties and demonstrate great potential for replacing conventional silicon(Si)semiconductors with WBG technology,pushing the boundaries of power devices to handle higher blocking voltages,switching frequencies,output power levels,and operating temperatures.However,tradeoffs in switching performance and converter efficiency when substituting GaN devices for Si and SiC counterparts are not well-defined,especially in a cascode configuration.Additional research with further detailed investigation and analysis is necessitated for medium-voltage GaN devices in power converter applications.Therefore,the aim of this research is to experimentally investigate the impact of emerging 650/900 V cascode GaN devices on bidirectional dc-dc converters that are suitable for energy storage and distributed renewable energy systems.Dynamic characteristics of Si,SiC,and cascode GaN power devices are examined through the double-pulse test(DPT)circuit at different gate resistance values,device currents,and DC bus voltages.Furthermore,the switching behavior and energy loss as well as the rate of voltage and current changes over the time are studied and analyzed at various operating conditions.A 500 W experimental converter prototype is implemented to validate the benefits of cascode GaN devices on the converter operation and performance.Comprehensive analysis of the power losses and efficiency improvements for Si-based,SiC-based,and GaN-based converters are performed and evaluated as the switching frequency,working temperature,and output power level are in-creased.The experimental results reveal significant improvements in switching performance and energy efficiency from the emerging cascode GaN devices in the bidirectional converters.

Characterization of Self-driven Cascode-Configuration Synchronous Rectifiers

This paper presents a cascode configuration synchronous rectifier device based on silicon MOSFET and Schottky diode,which can replace traditional power diode directly.This structure has self-driven ability with simple external circuit,and the conduction characteristic is preferable to a power diode.Static characterization and switching behavior analysis of proposed structure are conducted in this paper.The switching process is illustrated in detail using real model which considers the parasitic inductances and the nonlinearity of junction capacitors.The real time internal voltage and current value during switching transition are deduced with the equivalent circuit.To validate the analysis,two voltage specification rectifiers are built.Finally,double-pulse test results and the practical design example verify the performance advantages of proposed structure.

A CMOS 4.1 GHZ TWO-STAGE CASCODE LNA WITH ESD PROTECTION

A 4.1 GHz two-stage cascode Low-Noise Amplifier(LNA) with Electro-Static Discharge(ESD) protection is presented in this paper.The LNA has been optimized using ESD and LNA co-design methodology to achieve a good performance.Post-layout simulation results exhibit a forward gain(S21) of about 21 dB, a reverse isolation(S12) of less than-18 dB, an input return loss(S11) of less than-16 dB, and an output return loss(S22) of less than-17 dB.Moreover, the Noise Figure(NF) is 2.6 dB.This design is implemented in TSMC0.18μm RF CMOS technology and the die area is 0.9 mm×0.9 mm.

On the Operation of CMOS Active-Cascode Gain Stage

An s-domain analysis of the full dynamics of the pole-zero pair (frequency doublet) associated with the broadly used CMOS active-cascode gain-enhancement technique is presented. Quantitative results show that three scenarios can arise for the settling behavior of a closed-loop active-cascode operational amplifier depending on the relative locations of the unity-gain frequencies of the auxiliary and the main amplifiers. The analysis also reveals that, although theoretically possible, it is practically difficult to achieve an exact pole-zero cancellation. The analytical results presented here provide theoretical guidelines to the design of CMOS operational amplifiers using this technique.

Study on irradiation effect and damage mechanism in cascode GaN HEMT irradiated by 10 MeV electron

This study investigated the irradiation effect of cascode-structure GaN HEMT(High Electron Mobility Transistor)devices,employing high-energy electrons with an energy of 10 MeV and irradiation doses ranging from 5 to 80 Mrad(Si).The variation of electrical properties of the device under annealing condition was analyzed.Geant4 and TCAD simulations were used to analyze the irradiation effect and damage mechanisms.The results show that the threshold voltage has obvious negative drift and the drain current increases after irradiation.The threshold voltage deviation amplitude of the device increases with the increase of irradiation dose,and the maximum deviation is 1.41V.Annealing at high temperatures(80℃,120℃ and 145℃)partially restores the electrical properties,with a 0.49 V restoration in threshold voltage at 145℃.Geant4 simulations reveal that enhanced Si MOSFET is more susceptible to total dose effects.TCAD simulations of enhanced Si MOSFET devices demonstrate an increase in electric field intensity,trapped electron concentration,and hole concentration in Si and SiO_(2) layers with the increase of irradiation dose.These findings can provide support for the space application and irradiation hardening of cascode GaN HEMT devices.

Simplified Analytical Model for Estimation of Switching Loss of Cascode GaN HEMTs in Totem-pole PFC Converters

A practical analytical model to calculate the switching loss of cascode gallium nitride high electron mobility transistors(GaN HEMTs)is proposed.To facilitate analysis and application,the transmission delays introduced by Si MOSFET and interconnection inductances are ignored in modeling.Meanwhile,the nonlinear junction capacitances of the device and circuit stray inductances are also incorporated to increase the accuracy of the model.The turn-on and turn-off switching processes are described in detail and the simplified equations can be easily solved by using mathematical tools.Based on the analytical model,loss evaluation of totem-pole PFC converter is introduced briefly.Finally,the accuracy of the model is validated by comparing the calculated loss and converter’s efficiency with experiment results.Peak efficiency of 99.26%is achieved for a 3.6 kW single phase CCM Totem-Pole PFC AC/DC converter switching at 50 kHz based on 650 V cascode GaN HEMTs.

Structural parameters improvement of an integrated HBT in a cascode configuration opto-electronic mixer

We analyze an integrated electrically pumped opto-electronic mixer, which consists of two InP/GalnAs hetero junction bipolar transistors （HBT）, in a cascode configuration. A new HBT with modified physical structure is proposed and simulated to improve the frequency characteristics of a cascode mixer. For the verification and calibrating software simulator, we compare the simulation results of a typical HBT, before modifying it and com paring it with empirical reported experiments. Then we examine the simulator on our modified proposed HBT to prove its wider frequency characteristics with better flatness and acceptable down conversion gain. Although the idea is examined in several GHz modulation, it may easily be extended to state of the art HBT cascode mixers in much higher frequency range.

A W-band two-stage cascode amplifier with gain of 25.7 dB

AW-bandtwo-stageamplifierMMIChasbeendevelopedusingafullypassivated 2 × 20 μm gate-width and 0.15 μm gate-length InP-based high electron mobility transistor （HEMT） technology. The two-stage amplifier has been realized in combination with a coplanar waveguide technique and cascode topology, thus leading to a compact chip-size of 1.85 × 0.932 mm^2 and an excellent small-signal gain of 25.7 dB at 106 GHz. Additionally, an inter-digital coupling capacitor blocks low-frequency signal, thereby enhancing the stability of the amplifier. The successful design of the two-stage amplifier MMIC indicates that InP HEMT technology has a great potential for W-band applications.

Design of a 0.5 V CMOS cascode low noise amplifier for multi-gigahertz applications

This paper presents the design of 0.5 V multi-gigahertz cascode CMOS LNA for low power wireless communication. By splitting the direct current through conventional cascode topology, the constraint of stacking- MOS structure for supply voltage has been removed and based on forward-body-bias technology, the circuit can operate at 0.5 V supply voltage. Design details and RF characteristics have been investigated in this paper. To verify the investigation, a 0.5 V 5.4 GHz LNA has been fabricated through 0.18 μm CMOS technology and measured. Measured results show that it obtains 9.1 dB gain, 3 dB NF with 0.5 V voltage and 2.5 mW power dissipation. The measured IIP3 is -3.5 dBm. Compared with previously published cascode LNA, it achieves the lowest supply voltage and lowest power dissipation with competitive RF performances.

Cascode型GaN HEMT发展及其特性应用探讨

新能源并网技术的进步,对电力电子器件的性能提出了更高的要求。传统电力电子器件逐步逼近理论极限。宽禁带半导体氮化镓材料(GaN)是第三代半导体材料的典型代表,有许多硅材料不具备的优异性能,在军事、民用等领域应用前景广阔。近年来,GaN高电子迁移率晶体管(HEMT)被相继推出,受到广泛的关注。氮化镓高电子迁移率晶体管(GaN HEMT)在电力电子领域已经应用。高压共源共栅(Cascode)型GaN HEMT,实现了在高压场合,可以应用GaN器件。本文对Cascode型GaN HEMT的全范围输出伏安特性进行研究,分析其工作模态及条件,以及在单相全桥逆变器电路中的应用。