A chip-level space-time equalization receiver scheme is proposed for multiple-input multiple-output high-speed downlink packet access (MIMO HSDPA) systems to jointly combat the co-channel interference and the inter-co...A chip-level space-time equalization receiver scheme is proposed for multiple-input multiple-output high-speed downlink packet access (MIMO HSDPA) systems to jointly combat the co-channel interference and the inter-code interference. A fractional sample equalizer is also derived to further improve the performance of the receiver. Performance analysis and the calculation of the output signal to interference ratio (SINR) at each receiver antenna are presented to help direct the design of equalization weight in a more optimal manner. System simulations demonstrate the significant performance gain over conventional Rake receiver and high potential of MIMO HSDPA for high-data-rate packet transmission.展开更多
文摘A chip-level space-time equalization receiver scheme is proposed for multiple-input multiple-output high-speed downlink packet access (MIMO HSDPA) systems to jointly combat the co-channel interference and the inter-code interference. A fractional sample equalizer is also derived to further improve the performance of the receiver. Performance analysis and the calculation of the output signal to interference ratio (SINR) at each receiver antenna are presented to help direct the design of equalization weight in a more optimal manner. System simulations demonstrate the significant performance gain over conventional Rake receiver and high potential of MIMO HSDPA for high-data-rate packet transmission.
