Quantum algorithm for minimum dominating set problem with circuit design

Using quantum algorithms to solve various problems has attracted widespread attention with the development of quantum computing.Researchers are particularly interested in using the acceleration properties of quantum algorithms to solve NP-complete problems.This paper focuses on the well-known NP-complete problem of finding the minimum dominating set in undirected graphs.To expedite the search process,a quantum algorithm employing Grover’s search is proposed.However,a challenge arises from the unknown number of solutions for the minimum dominating set,rendering direct usage of original Grover’s search impossible.Thus,a swap test method is introduced to ascertain the number of iterations required.The oracle,diffusion operators,and swap test are designed with achievable quantum gates.The query complexity is O(1.414^(n))and the space complexity is O(n).To validate the proposed approach,qiskit software package is employed to simulate the quantum circuit,yielding the anticipated results.

SOME COMBINATORIAL OPTIMIZATION PROBLEMS ARISING FROM VLSI CIRCUIT DESIGN

This paper is basically a survey to show a number of combinatorial optimization problems arising from VLSI circuit design. Some of them including the existence problem, minimax problem, net representation, bend minimization, area minimization, placement problem, routing problem, etc. are especially discussed with new results and theoretical ideas for treating them. Finally, a number of problems for further research are mentioned.

Concise Modeling of Amorphous Dual-Gate In-Ga-Zn-O Thin-Film Transistors for Integrated Circuit Designs

An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors（a-IGZO TFTs）with dual-gate structures is developed.The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges,which are controlled by gate voltage.It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance（C_（TI）/C_（BI））.Incorporating the proposed model with Verilog-A,a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations.Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.

Applications of modularized circuit designs in a new hyper-chaotic system circuit implementation

Modularized circuit designs for chaotic systems are introduced in this paper.Especially,a typical improved modularized design strategy is proposed and applied to a new hyper-chaotic system circuit implementation.In this paper,the detailed design procedures are described.Multisim simulations and physical experiments are conducted,and the simulation results are compared with Matlab simulation results for different system parameter pairs.These results are consistent with each other and they verify the existence of the hyper-chaotic attractor for this new hyper-chaotic system.

Microwave Integrated Circuit Design Handbook

作者:Reinmut K.Hoffmann(1984 IEEE微波奖获得者) 出版:Artech House公司(美国)1987年本书给出适于微波工程师和研究人员应用的有关MIC方面的基础技术、电性能和设计。侧重于电性能分析和设计,强调应用。对于每一种设计技术和应用均作出较清楚的叙述和完整的处理。本书尽量给出电路的物理描述,避免过于冗长的数学公式,内容包含对下列议题的详细评述与研讨:

Hydraulic Circuit Design and Dynamic Learning Using Case-based Reasoning

This paper describes the design and implementation of a hydraulic circuit design system using case-based reasoning (CBR) paradigm from AI community The domain of hydraulic circuit design and case-based reasoning are briefly reviewed Then a proposed methodology in compuer-aided circuit design and dynamic leaning with the use of CBR is described Finally an application example is selected to illustrate the ussfulness of applying CBR in hydraulic circuit design with leaming.

Toward predictable universal genetic circuit design

In thepast 2decades,synthetic biologists have applied systematic engineering principles to genetic circuit design to devise biological systems with bespoke behaviors,such as Boolean logic gates,signal filters,oscillators,state machines,perceptrons,and genetic controllers[1,2].Following a bottom-up strategy,the genetic circuits are designed by assembling a set of well-characterized biological components,or genetic parts[3],and optimized through the iterative Design-Build-Test-Learn(DBTL)cycles.

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

A review on the design of ternary logic circuits

A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

A Novel Self-adaptive Circuit Design Technique Based on Evolvable Hardware

Since traditional fault tolerance methods of electronic systems are based on redundant fault tolerance technique,and their structures are fixed when circuits are designed,the self-adaptive ability is limited.In order to solve these problems,a novel circuit self-adaptive design technique based on evolvable hardware(EHW)is proposed.It features robustness,self-organization and self-adaption.It can be adapted to a complex environment through dynamic configuration of the circuit.In this paper,the proposed technique simulated.The consumption of hardware resources and the number of convergence iterations researched.The effectiveness and superiority of the proposed technique are verified.The designed circuit has the ability of resistible redundant-state interference(RRSI).The proposed technique has a broad application prospect,and it has great significance.

A fuzzy-logic-based approach to accurate modeling of a double gate MOSFET for nanoelectronic circuit design

The double gate （DG） silicon MOSFET with an extremely short-channel length has the appropriate fea- tures to constitute the devices for nanoscale circuit design. To develop a physical model for extremely scaled DG MOSFETs, the drain current in the channel must be accurately determined under the application of drain and gate voltages. However, modeling the transport mechanism for the nanoscale structures requires the use of overkill meth- ods and models in terms of their complexity and computation time （self-consistent, quantum computations ）. Therefore, new methods and techniques are required to overcome these constraints. In this paper, a new approach based on the fuzzy logic computation is proposed to investigate nanoscale DG MOSFETs. The proposed approach has been implemented in a device simulator to show the impact of the proposed approach on the nanoelectronic cir- cuit design. The approach is general and thus is suitable for any type ofnanoscale structure investigation problems in the nanotechnology industry.

DESIGN OF LIGHTWEIGHT PUF CIRCUIT BASED ON SELECTABLE CROSS-COUPLED INVERTERS

By analyzing the principle of process variations, a lightweight Physical Unclonable Function （PUF） circuit based on selectable cross-coupled inverters is proposed in this paper. Firstly, selectable cross-coupled inverters are chosen for two delay paths. Simultaneously, the circuit takes challenge signal to control each delay path. The PUF cell circuit is implemented in Semiconductor Manufacturing International Corporation （SMIC） 65 nm CMOS technology and the layout area is 2.94μm × 1.68μm. Then the 64-bit PUF circuit is achieved with the cascade connection of cell circuits. The simulation results show that the randomness is 49.4% and the reliability is 96.5%. Compared to the other works, this PUF circuit improves the encrypt performance and greatly reduces the area.

Design of Digital Circuit Experiment Course Based on FPGA

With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledge meet the needs of the industry, the school adopts the FPGA experimental platform to carry out teaching reform from the two aspects of platform and experiment, and carry out reasonable experimental planning to enrich the experimental content. In this paper, the traditional knowledge points of logic algebra, trigger, timer, counter, decoder and digital tube are organically combined, and the digital clock system is designed and realized. The practice shows that the combination of modern design method and traditional digital circuit teaching method can play a good teaching effect. In this way, students can also fully learn, understand and skillfully use the new technology in the experiment, and in the process of building a comprehensive understanding of digital circuits.

A new Rsslor hyperchaotic system and its realization with systematic circuit parameter design

Based on two modified Rosslor hyperchaotic systems, which are derived from the chaotic Rosslor system by introducing a state feedback controller, this paper proposes a new switched Rosslor hyperchaotic system. The switched system contains two different hyperchaotic systems and can change its behaviour continuously from one to another via a switching function. On the other hand, it presents a systematic method for designing the circuit of realizing the proposed hyperchaotic system. In this design, circuit state equations are written in normalized dimensionless form by rescaling the time variable. Furthermore, an analogous circuit is designed by using the proposed method and built for verifying the new hyperchaos and the design method. Experimental results show a good agreement between numerical simulations and experimental results.

LOW-FREQUENCY LOW-NOISE CIRCUITS DESIGN USING AN E_n-I_n MODEL

In view of the limitations of a Rn-Gn model in the low frequency range and the defects of an En-In model in common use now, this paper builds a complete En-In model according to the theory of random harmonic. The parameters for the low-noise design such as the equivalent input noisy voltage Ens, the optimum source impedance Zsopt and the minimum noise figure Fmin can be calculated accurately by using this En-In model because it considers the coherence between the noise sources fully. Moreover, this paper points out that it will cause the maximum 30% miscalculation when neglecting the effects of the correlation coefficient 7. Using the series-series circuits as an example, this paper discusses the methods for the En-In noise analysis of electronic circuits preliminarily and demonstrates its correctness through the comparison between the simulated and measured results of the minimum noise figure Fmin of a single current series negative feedback circuit.

Evolutionary Design of Fault-Tolerant Digital Circuit Based on Cartesian Genetic Programming

In many areas, reliability of the digital circuits has become the key factor to restrict circuit development. Fault-tolerant design is the commonly used method to improve the reliability of digital circuits. The current fault-tolerant design methods are based on triple modular redundancy( TMR) or multiple modular redundancy( MMR). These redundancy designs rely on the experience of the designers,and the designed circuits have poor adaptabilities to a complex environment. However, evolutionary design of digital circuits does not rely on prior knowledge. During the evolution, some novel and optimal circuit topologies can be found, and the evolved circuits can feature strong adaptive capacities. Based on Cartesian genetic programming( CGP), a novel method for designing fault-tolerant digital circuits by evolution is proposed,key steps of the evolution are introduced,influences of function sets on evolution are investigated,and as a preliminary result,an evolved full adder with high fault-tolerance is shown.

The Design of Circuit for Checking Short in HT-7U Superconducting Tokamak Device

The tokamak HT-7U project has been funded as a Chinese national project since 1998. The main object of the project is to build a nuclear fusion experimental device with divertor configuration, which is designed by the Institute of Plasma Physics, the Chinese Academy of Sciences (ASIPP). It is a full superconducting device, consisting of superconducting toroidal field (TF) coils and superconducting poloidal field (PF) coil. During the operation of the device, the operational parameter of device should be checked by technical diagnosis. This paper describes the design of circuit for checldng short between every two parts of the HT7U device. The main contents of design include circuit of data acquisition and data processing of computer.

A UNIFIED THEORY FOR DESIGNING ANDANALYZING BOTH SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.

无刷双馈电机研究综述与展望

无刷双馈电机具有结构可靠、变频器容量小等优势,非常适合灵活运行于防爆、易燃等特殊或极端工况,近年来受到广泛关注。该文根据无刷双馈电机的基本工作原理,明确了该类电机的命名原则与规范名称;总结了现有定转子方案的结构及性能特点,综合考虑性能指标与结构工艺,提出了转子双套绕组的发展方向;梳理了无刷双馈电机的稳态等效电路模型及基于各类数学模型的优化设计方法,针对现存难以完整考虑不同转速工况性能的不足,阐明了利用新型同步-异步相串联等效电路进行优化设计的思路;对比分析了经典及新近出现的无刷双馈电机控制系统拓扑和控制策略特点,面向典型电动、发电工况建立了完整的电机及控制系统。最后,对无刷双馈电机的上述理论研究问题及工业应用的发展方向进行了总结阐述,为该类电机的深入研究及加快推广应用提供参考和指导。