For time-of-flight(TOF)light detection and ranging(LiDAR),a three-channel high-performance transimpedance amplifier(TIA)with high immunity to input load capacitance is presented.A regulated cascade(RGC)as the input st...For time-of-flight(TOF)light detection and ranging(LiDAR),a three-channel high-performance transimpedance amplifier(TIA)with high immunity to input load capacitance is presented.A regulated cascade(RGC)as the input stage is at the core of the complementary metal oxide semiconductor(CMOS)circuit chip,giving it more immunity to input photodiode detectors.A simple smart output interface acting as a feedback structure,which is rarely found in other designs,reduces the chip size and power consumption simultaneously.The circuit is designed using a 0.5μm CMOS process technology to achieve low cost.The device delivers a 33.87 dB?transimpedance gain at 350 MHz.With a higher input load capacitance,it shows a-3 dB bandwidth of 461 MHz,indicating a better detector tolerance at the front end of the system.Under a 3.3 V supply voltage,the device consumes 5.2 mW,and the total chip area with three channels is 402.8×597.0μm2(including the test pads).展开更多
This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process.Multiple bandwidth enhancement techniques,including input bonding wire,input series on-chip i...This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process.Multiple bandwidth enhancement techniques,including input bonding wire,input series on-chip inductive peak-ing and negative capacitance compensation,are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device,achieving an overall bandwidth enhancement ratio of 8.5.The electrical measure-ment shows TIA achieves 58 dBΩup to 12.7 GHz with a 180-fF off-chip photodetector.The optical measurement demonstrates a clear open eye of 20 Gb/s.The TIA dissipates 4 mW from a 1.2-V supply voltage.展开更多
A differential cross-coupled regulated cascode(RGC)transimpedance amplifier(TIA)is proposed. The theory of multi-stage common-source(CS) configuration as an auxiliary amplifier to enhance the bandwidth and output impe...A differential cross-coupled regulated cascode(RGC)transimpedance amplifier(TIA)is proposed. The theory of multi-stage common-source(CS) configuration as an auxiliary amplifier to enhance the bandwidth and output impedance of RGC topology is analyzed. Additionally, negative Miller capacitance and shunt active inductor compensation are exploited to further expand the bandwidth. The proposed RGC TIA is simulated based on UMC 0.18 μm standard CMOS process. The simulation results demonstrate that the proposed TIA has a high transimpedance of 60.5 d B?, and a-3 d B bandwidth of 5.4 GHz is achieved for 0.5 p F input capacitance. The average equivalent input noise current spectral density is about 20 p A/Hz^(1/2) in the interested frequency, and the TIA consumes 20 m W DC power under 1.8 V supply voltage. The voltage swing is 460 m V pp, and the saturation input current is 500 μA.展开更多
As the front-end preamplifiers in optical receivers, transimpedance amplifiers （TIAs） are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time,...As the front-end preamplifiers in optical receivers, transimpedance amplifiers （TIAs） are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range （DR） to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the -3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the -3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage.展开更多
A zero-pole cancellation transimpedance amplifier（TIA）has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input pa...A zero-pole cancellation transimpedance amplifier（TIA）has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration.Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ωfor 1.5 pF photodiode capaci- tance,with a gain-bandwidth product of 3.4 THz·Ω.Even with 2 pF photodiode capacitance,the bandwidth exhibits a decline of only 300 MHz,confirming the mechanism of the zero-pole cancellation configuration.The input resis- tance is 50Ω,and the average input noise current spectral density is 9.7 pA/√ Hz.Testing results shows that the eye diagram at 1 Gb/s is wide open.The chip dissipates 17 mW under a single 3.3 V supply.展开更多
Background The beam intensity of the High Intensity Heavy-ion Accelerator Facility(HIAF)is converted into current sig-nals by beam intensity detectors and then processed by front-end electronics.The performance of the...Background The beam intensity of the High Intensity Heavy-ion Accelerator Facility(HIAF)is converted into current sig-nals by beam intensity detectors and then processed by front-end electronics.The performance of the front-end electronics affects the measurement accuracy of the accelerator.Purpose To design front-end electronics to readout the current signals from a beam intensity detector.Methods A programmable transimpedance amplifier(TIA)converts current signals into voltage signals and amplify the signals.An analog-to-digital converter(ADC)converts analog signals into digital signals under the control of ZYNQ7015.Results and conclusion An integrated front-end electronics system was designed and verified.The electronics could collect and process current signals from 40 pA to 4 mA.The system had a higher dynamic range than traditional beam intensity measuring electronics.展开更多
设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 m Vpp的差分电压信号。该全差分前置放大电路采用0.18μm CMOS工艺进...设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 m Vpp的差分电压信号。该全差分前置放大电路采用0.18μm CMOS工艺进行设计,当光电二极管电容为250 f F时,该光接收机前置放大电路的跨阻增益为92 d BΩ,-3 d B带宽为7.9 GHz,平均等效输入噪声电流谱密度约为23 p A/(0~8 GHz)。该电路采用电源电压为1.8 V时,跨阻放大器功耗为28 m W,限幅放大器功耗为80 m W,输出缓冲器功耗为40 m W,其芯片面积为800μm×1 700μm。展开更多
为抑制干扰和提高电路的线性,采用0.13μm RF CMOS工艺设计了一款无需声表滤波器的射频前端电路系统.该设计采用一种新的带干扰消除环路可变增益低噪声跨导放大器、25%占空比本振信号的无源混频器和互阻放大器架构来实现抗干扰、低噪声...为抑制干扰和提高电路的线性,采用0.13μm RF CMOS工艺设计了一款无需声表滤波器的射频前端电路系统.该设计采用一种新的带干扰消除环路可变增益低噪声跨导放大器、25%占空比本振信号的无源混频器和互阻放大器架构来实现抗干扰、低噪声、高线性的射频前端.流片和测试结果表明:该电路抑制带外强干扰达20 d B以上,在2.4 GHz可实现44.98 d B增益和2.03 d B噪声系数,同时获得-7 d Bm的输入三阶互调截点和+72 d Bm的输入二阶互调截点,实现了无需声表滤波器和抗干扰特性;整个射频前端供电电压为1.2 V,功耗为36 m A.展开更多
文摘For time-of-flight(TOF)light detection and ranging(LiDAR),a three-channel high-performance transimpedance amplifier(TIA)with high immunity to input load capacitance is presented.A regulated cascade(RGC)as the input stage is at the core of the complementary metal oxide semiconductor(CMOS)circuit chip,giving it more immunity to input photodiode detectors.A simple smart output interface acting as a feedback structure,which is rarely found in other designs,reduces the chip size and power consumption simultaneously.The circuit is designed using a 0.5μm CMOS process technology to achieve low cost.The device delivers a 33.87 dB?transimpedance gain at 350 MHz.With a higher input load capacitance,it shows a-3 dB bandwidth of 461 MHz,indicating a better detector tolerance at the front end of the system.Under a 3.3 V supply voltage,the device consumes 5.2 mW,and the total chip area with three channels is 402.8×597.0μm2(including the test pads).
基金supported in part by the National NaturalScience Foundation of China under Grant 62074074in part by Natural Science Foundation of Guangdong Province under Grant 2021A1515011266in part by the Science and Technology Plan of Shenzhen under Grants JCYJ20190809142017428 and JCYJ20200109141225025。
文摘This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process.Multiple bandwidth enhancement techniques,including input bonding wire,input series on-chip inductive peak-ing and negative capacitance compensation,are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device,achieving an overall bandwidth enhancement ratio of 8.5.The electrical measure-ment shows TIA achieves 58 dBΩup to 12.7 GHz with a 180-fF off-chip photodetector.The optical measurement demonstrates a clear open eye of 20 Gb/s.The TIA dissipates 4 mW from a 1.2-V supply voltage.
基金Supported by the National Natural Science Foundation of China(No.61474081)
文摘A differential cross-coupled regulated cascode(RGC)transimpedance amplifier(TIA)is proposed. The theory of multi-stage common-source(CS) configuration as an auxiliary amplifier to enhance the bandwidth and output impedance of RGC topology is analyzed. Additionally, negative Miller capacitance and shunt active inductor compensation are exploited to further expand the bandwidth. The proposed RGC TIA is simulated based on UMC 0.18 μm standard CMOS process. The simulation results demonstrate that the proposed TIA has a high transimpedance of 60.5 d B?, and a-3 d B bandwidth of 5.4 GHz is achieved for 0.5 p F input capacitance. The average equivalent input noise current spectral density is about 20 p A/Hz^(1/2) in the interested frequency, and the TIA consumes 20 m W DC power under 1.8 V supply voltage. The voltage swing is 460 m V pp, and the saturation input current is 500 μA.
基金supported by the National Natural Science Foundation of China(Nos.61376033,61006028)the National High-Tech Program of China(Nos.2012AA012302,2013AA014103)the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory
文摘As the front-end preamplifiers in optical receivers, transimpedance amplifiers （TIAs） are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range （DR） to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the -3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the -3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage.
基金supported by the National Natural Science Foundation of China(Nos.60536030,60502005)the National High Technology Research and Development Program of China(Nos.2007AA01Z2A5,2006AA01Z239,2007AA03Z454)
文摘A zero-pole cancellation transimpedance amplifier（TIA）has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration.Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ωfor 1.5 pF photodiode capaci- tance,with a gain-bandwidth product of 3.4 THz·Ω.Even with 2 pF photodiode capacitance,the bandwidth exhibits a decline of only 300 MHz,confirming the mechanism of the zero-pole cancellation configuration.The input resis- tance is 50Ω,and the average input noise current spectral density is 9.7 pA/√ Hz.Testing results shows that the eye diagram at 1 Gb/s is wide open.The chip dissipates 17 mW under a single 3.3 V supply.
基金This research work is supported by National Nature Science Foundation of China under Grant No.E911010301.
文摘Background The beam intensity of the High Intensity Heavy-ion Accelerator Facility(HIAF)is converted into current sig-nals by beam intensity detectors and then processed by front-end electronics.The performance of the front-end electronics affects the measurement accuracy of the accelerator.Purpose To design front-end electronics to readout the current signals from a beam intensity detector.Methods A programmable transimpedance amplifier(TIA)converts current signals into voltage signals and amplify the signals.An analog-to-digital converter(ADC)converts analog signals into digital signals under the control of ZYNQ7015.Results and conclusion An integrated front-end electronics system was designed and verified.The electronics could collect and process current signals from 40 pA to 4 mA.The system had a higher dynamic range than traditional beam intensity measuring electronics.
文摘设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 m Vpp的差分电压信号。该全差分前置放大电路采用0.18μm CMOS工艺进行设计,当光电二极管电容为250 f F时,该光接收机前置放大电路的跨阻增益为92 d BΩ,-3 d B带宽为7.9 GHz,平均等效输入噪声电流谱密度约为23 p A/(0~8 GHz)。该电路采用电源电压为1.8 V时,跨阻放大器功耗为28 m W,限幅放大器功耗为80 m W,输出缓冲器功耗为40 m W,其芯片面积为800μm×1 700μm。
文摘为抑制干扰和提高电路的线性,采用0.13μm RF CMOS工艺设计了一款无需声表滤波器的射频前端电路系统.该设计采用一种新的带干扰消除环路可变增益低噪声跨导放大器、25%占空比本振信号的无源混频器和互阻放大器架构来实现抗干扰、低噪声、高线性的射频前端.流片和测试结果表明:该电路抑制带外强干扰达20 d B以上,在2.4 GHz可实现44.98 d B增益和2.03 d B噪声系数,同时获得-7 d Bm的输入三阶互调截点和+72 d Bm的输入二阶互调截点,实现了无需声表滤波器和抗干扰特性;整个射频前端供电电压为1.2 V,功耗为36 m A.
