To solve the issue of downloading speed and application scenarios limitation of current JTAGLink debugger, this paper presents a new scheme of ARM debugger with the feature of Ethemet interface implemented by pure har...To solve the issue of downloading speed and application scenarios limitation of current JTAGLink debugger, this paper presents a new scheme of ARM debugger with the feature of Ethemet interface implemented by pure hardware logic design. This paper outlines the principle of the scheme, blocks of logic design, and protocols design. The scheme provides higher downloading speed, wider flexibility on application, and improves work efficiency evidently. Key words： JTAGLink Debugger; Ethernet; FPGA; Logic Design展开更多
The objective of this contribution is to present expositive review content on currently available experimental tools/services/concepts used for most emerging field Wireless Sensor Network that has capability to change...The objective of this contribution is to present expositive review content on currently available experimental tools/services/concepts used for most emerging field Wireless Sensor Network that has capability to change many of the Information Communication aspects in the upcoming era. Currently due to high cost of large number of sensor nodes most researches in wireless sensor networks area is performed by using these experimental tools in various universities, institutes, and research centers before implementing real one. Also the statistics gathered from these experimental tools can be realistic and convenient. These experimental tools provide the better option for studying the behavior of WSNs before and after implementing the physical one. In this contribution 63 simulators/simulation frameworks, 14 emulators, 19 data visualization tools, 46 testbeds, 26 debugging tools/services/concepts, 10 code-updation/reprogramming tools and 8 network monitors has been presented that are used worldwide for WSN researches.展开更多
文摘To solve the issue of downloading speed and application scenarios limitation of current JTAGLink debugger, this paper presents a new scheme of ARM debugger with the feature of Ethemet interface implemented by pure hardware logic design. This paper outlines the principle of the scheme, blocks of logic design, and protocols design. The scheme provides higher downloading speed, wider flexibility on application, and improves work efficiency evidently. Key words： JTAGLink Debugger; Ethernet; FPGA; Logic Design
文摘The objective of this contribution is to present expositive review content on currently available experimental tools/services/concepts used for most emerging field Wireless Sensor Network that has capability to change many of the Information Communication aspects in the upcoming era. Currently due to high cost of large number of sensor nodes most researches in wireless sensor networks area is performed by using these experimental tools in various universities, institutes, and research centers before implementing real one. Also the statistics gathered from these experimental tools can be realistic and convenient. These experimental tools provide the better option for studying the behavior of WSNs before and after implementing the physical one. In this contribution 63 simulators/simulation frameworks, 14 emulators, 19 data visualization tools, 46 testbeds, 26 debugging tools/services/concepts, 10 code-updation/reprogramming tools and 8 network monitors has been presented that are used worldwide for WSN researches.
