Dual DVCC Based Voltage-Mode Digitally Programmable Biquadratic Filter

The recent advances in IC technology have led to the trend of designing hybrid systems to benefit both analog and the digital domain. Among analog circuits, multifunctional filter along with multiphase oscillator constitutes a building block of critical importance. In this paper, a digitally reconfigurable multi-input-multi-output voltage mode multifunctional biquadratic filter has been presented. The circuit comprises of two differential voltage current conveyors (DVCCs), two grounded capacitors and two floating resistors. The digital controllability is incorporated using a current-summing network (CSN). Tunability of quality factor is achieved by the use of a 3-bit digital control word while keeping the resonant frequency constant. PSPICE simulations using TSMC 0.25 μm CMOS technology have been performed to validate the theoretically predicted results.

A Method of Digitally Reconstructed Radiographs Based on Medical CT Images

A complete and detail method is described to get digitally reconstructed radiographs （DRRs）. Casting rays to traverse CT images, computing CT values of resample points by interpolation, then converting CT value to its attenuation coefficient by using simplified segment function. Finally, DRRs enhancement is made to get the better display of region of interest （ROI）, and a new way is adopted to adjust the customization coefficient. The experimental results show that the proposed method is effective in generating the satisfied DRRs.

Digitally Programmable Voltage Mode Universal Filters—A Minimal Realization

Three voltage mode universal filter biquads using digitally programmable second generation current conveyor (CCII) are presented in this paper. Salient features of proposed filter configurations include realization of all the filter functions except allpass, independently programmable filter parameters, no component matching constraint and low sensitivity figure. Component count of proposed filter configurations is proved to be minimal for offering aforementioned set of features. Workability of proposed circuit is verified by including the SPICE simulations.

IMPROVING THE FREQUENCY RESOLUTION OF DIGITALLY SYNTHESIZED PERIODIC SIGNALS BY A SEQUENTIAL ADDRESSING SCHEME

In the digital synthesis of wideband periodic signals using an Arbitrary Waveform Gen-erator(AWG),the frequency resolution and spectral complexity of the synthesized signals are com-monly limited by the memory capacity and clock frequency of the AWG.This paper proposes a novel sequential addressing scheme and then presents several sequences to improve the frequency resolution of the synthesized periodic signals without changing their spectral envelopes and basic time-domain characteristics under the condition of a fixed memory capacity and a fixed clock fre-quency.The main idea of the scheme is using the address generator in an AWG to program and produce addresses to read fixed waveform data in variable order,and thus to generate waveforms of various periods and profiles.The scheme is applied in simulating signal scenarios for military com-munication countermeasure experiments,and achieves high performance.

Digitally calibrated broadband dual-comb gases absorption spectral measurements

From the perspective of error compensation in the sampling process, a digital calibration algorithm was studied for the processing of spectral data in dual-comb spectroscopy. In this algorithm, dynamic adaptation to phase fluctuations maintained constant measurement results of spectral line positions and intensities. A mode-resolved broadband absorption spectrum was obtained over the full-spectral range of the comb with a Hertz linewidth of radio frequency comb mode.The measured spectrum spanned over 10 THz, which covered the multiplexed absorption regions of mixed gases, such as CO2 and N2 O. The calibrated interferograms were also capable of direct coherent averaging in the time domain. The transmittance obtained deviated from the theoretical calculation by no more than 2% in the whole spectral span.

An efficient 3D cell-based discrete fracture-matrix flow model for digitally captured fracture networks

Complex hydraulic fracture networks are critical for enhancing permeability in unconventional reservoirs and mining indus-tries.However,accurately simulating the fluid flow in realistic fracture networks(compared to the statistical fracture net-works)is still challenging due to the fracture complexity and computational burden.This work proposes a simple yet efficient numerical framework for the flow simulation in fractured porous media obtained by 3D high-resolution images,aiming at both computational accuracy and efficiency.The fractured rock with complex fracture geometries is numerically constructed with a cell-based discrete fracture-matrix model(DFM)having implicit fracture apertures.The flow in the complex fractured porous media(including matrix flow,fracture flow,as well as exchange flow)is simulated with a pipe-based cell-centered finite volume method.The performance of this model is validated against analytical/numerical solutions.Then a lab-scale true triaxial hydraulically fractured shale sample is reconstructed,and the fluid flow in this realistic fracture network is simu-lated.Results suggest that the proposed method achieves a good balance between computational efficiency and accuracy.The complex fracture networks control the fluid flow process,and the opened natural fractures behave as primary fuid pathways.Heterogeneous and anisotropic features of fluid flow are well captured with the present model.

Digitally Mapping the Hydro-Topographical Context for Community Planning: A Case Study for the Upper Choapa River Watershed in Chile

Urban and non-urban settlements in many regions are usually located on the lands bordering shores, rivers, canals or streams. However, housing complexes, landfills, and areas for agriculture and mining are often assigned to locations without sufficiently detailed hydrographic information about subsequent potential if not actual flow and flooding impacts. Yet, for sustainable community planning with emphasis on harmonizing social, economic, environmental and institutional aspects, such information is essential. This article demonstrates how this need can in part be accommodated by way of digital elevation and wet-area modelling and mapping using the upper component of the Choapa watershed in Chile as a case study. The terrain of this area has sharply incised valleys, with communities, fields and roads strung narrowly along the Choapa River and its tributaries. Above these locations along the Estero de Los Pelambres near the Chile-Argentina border are major mining and mineral refining activities. This article provides modelling and mapping details about the wet-to-moist area zonation along the upper Choapa River valleys, and addresses some of the mining-induced changes from 2000 to 2010.

Digitally programmable organic light‐emitting tetrodes

Limited to the structure of traditional light‐emitting devices,electronic devices that can directly convert machine language into human visual information without introducing any back‐end circuit are still not easy to achieve.Based on a specially designed three‐phase co‐planar electrode structure,a new type of three‐phase alternating current driven organic light‐emitting device with the integration of emission and control functions,full‐color tunability and simple device structure is demonstrated in this study.We integrate the light‐emitting function of color‐tunable light‐emitting devices and the switching of three triodes in a single three phase organic light‐emitting device.The state control of luminous color and luminance intensity merely requires the introduction of a kind of machine language,that is an easy‐to‐program 6‐bit binary number coded digital signals.The color adjustable area covers 66%of the color triangle of the National Television System Committee.Such simple and easy‐to‐integrate light‐emitting system has great potential applications in the next‐generation man‐machine interface.

A low-power and low-phase-noise LC digitally controlled oscillator featuring a novel capacitor bank

A monolithic low-power and low-phase-noise digitally controlled oscillator （DCO） based on a symmetric spiral inductor with center-tap and novel capacitor bank was implemented in a 0.18 μm CMOS process with six metal layers. A third new way to change capacitance is proposed and implemented in this work. Results show that the phase noise at I MHz offset frequency is below -122.5 dBc/Hz while drawing a current of only 4.8 mA from a 1.8 V supply. Also, the DCO can work at low supply voltage conditions with a 1.6 V power supply and 4.1 mA supply current for the DCO＇s core circuit, achieving a phase-noise of-121.5 dBc/Hz at offset of 1 MHz. It demonstrates that the supply pushing of DCO is less than 10 MHz/V.

A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.

A digitally generated ultrafine optical frequency comb for spectral measurements with 0.01-pm resolution and 0.7-μs response time

Optical spectral measurements are crucial for optical sensors and many other applications,but the prevailing methods,such as optical spectrum analysis and tunable laser spectroscopy,often have to make compromises among resolution,speed,and accuracy.Optical frequency combs are widely used for metrology of discrete atomic and molecular spectral lines.However,they are usually generated by optical methods and have large comb spacing,which limits the resolution for direct sampling of continuous spectra.To overcome these problems,this paper presents an original method to digitally generate an ultrafine optical frequency comb(UFOFC)as the frequency ruler for spectral measurements.Each comb line provides one sampling point,and the full spectrum can be captured at the same time using coherent detection.For an experimental demonstration,we adopted the inverse fast Fourier transform to generate a UFOFC with a comb spacing of 1.46 MHz over a 10-GHz range and demonstrated its functions using a Mach–Zehnder refractive index sensor.The UFOFC obtains a spectral resolution of 0.01 pm and response time of 0.7 μs;both represent 100-fold improvements over the state of the art and could be further enhanced by several orders of magnitude.The UFOFC presented here could facilitate new label-free sensor applications that require both high resolution and fast speed,such as measuring binding kinetics and single-molecule dynamics.

Digitally controlled oscillator design with a variable capacitance XOR gate

A digitally controlled oscillator（DCO） using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-,five- and seven-stage DCO circuits have been designed using the proposed delay cell.The output frequency is controlled digitally with bits applied to the delay cells.The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW,respectively,with a change in the control word 111-000.The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW,respectively,with a change in the control word 11111-00000.Moreover,the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 mW,respectively, with a varying control word 1111111-0000000.The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements.

A digitally calibrated CMOS RMS power detector for RF automatic gain control

This paper presents the design and implementation of a digitally calibrated CMOS wideband radio frequency(RF) root-mean-square(RMS) power detector for high accuracy RF automatic gain control(AGC).The proposed RMS power detector demonstrates accurate power detection in the presence of process,supply voltage, and temperature(PVT) variations by employing a digital calibration scheme.It also consumes low power and occupies a small chip area.The measurement results show that the scheme improves the accuracy of the detector to better than 0.3 dB over the PVT variations and wide operating frequency range from 0.2 to 0.8 GHz.Implemented in a 0.18μm CMOS process and occupying a small die area of 263×214μm^2,the proposed digitally calibrated CMOS RMS power detector only consumes 1.6 mA in power detection mode and 2.1 mA in digital calibration mode from a 1.8 V supply voltage.

On-chip digitally tunable positive/negative dispersion controller using bidirectional chirped multimode waveguide gratings

A silicon-based digitally tunable positive/negative dispersion controller(DC)is proposed and realized for the first time using the cascaded bidirectional chirped multimode waveguide gratings(CMWGs),achieving positive and negative dispersion by switching the light propagation direction.A 1×2 Mach-Zehnder switch(MZS)and a 2×1 MZS are placed before and after to route the light path for realizing positive/negative switching.The device has Q stages of identical bidirectional CMWGs with a binary sequence.Thus the digital tuning is convenient and scalable,and the total dispersion accumulated by all the stages can be tuned digitally from−(2^(Q)−1)D0 to(2^(Q)−1)D_(0) with a step of D_(0) by controlling the switching states of all 2×2 MZSs,where D_(0) is the dispersion provided by a single bidirectional CMWG unit.Finally,a digitally tunable positive/negative DC with Q=4 is designed and fabricated.These CMWGs are designed with a 4-mm-long grating section,enabling the dispersion D_(0) of about 4.16 ps∕nm in a 20-nm-wide bandwidth.The dispersion is tuned from−61.53 to 63.77 ps∕nm by switching all MZSs appropriately,and the corresponding group delay is varied from−1021 to 1037 ps.

A programmable gain amplifier with digitally assisted DC offset calibration for a direct-conversion WLAN receiver

This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.

A digitally controlled PWM/PSM dual-mode DC/DC converter

A digitally controlled pulse width modulation/pulse skip modulation （PWM/PSM） dual-mode buck DC/DC converter is proposed. Its operation mode can be automatically chosen as continuous conduction mode （CCM） or discontinuous conduction mode （DCM）. The converter works in PSM at DCM and in 2 MHz PWM at CCM. Switching loss is reduced at a light load by skipping cycles. Thus high conversion efficiency is realized in a wide load current. The implementations of PWM control blocks, such as the ADC, the digital pulse width modulator （DPWM） and the loop compensator, and PSM control blocks are described in detail. The parameters of the loop compensator can be programmed for different external component values and switching frequencies, which is much more flexible than its analog rivals. The chip is manufactured in 0.13 μm CMOS technology and the chip area is 1.21 mm^2. Experimental results show that the conversion efficiency is high, being 90% at 200 mA and 67% at 20 mA. Meanwhile, the measured load step response shows that the proposed dual-mode converter has good stability.

A digitally controlled power amplifier with neutralization capacitors for Zigbee^(TM) applications

This paper presents a single chip CMOS power amplifier with neutralization capacitors for ZigbeeTM system according to IEEE 802.15.4. A novel structure with digital interface is adopted, which allows the output power ofa PA to be controlled by baseband signal directly, so there is no need for DAC. The neutralization capacitors will increase reverse isolation. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed power amplifier has a 13.5 dB power gain, 3.48 dBm output power and 35.1% PAE at P I dB point. The core area is 0.73 × 0.55 mm2.

Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

Digital controlled oscillators（DCOs） are the core of all digital phase locked loop（ADPLL） circuits. Here,DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology.Three,four and five bit controlled DCO with NMOS,PMOS and NMOS PMOS transistor switching networks are presented.A three-transistor XNOR gate has been used as the inverter which is used as the delay cell.Delay has been controlled digitally with a switch network of NMOS and PMOS transistors.The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740μW.A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998μW.Output frequency and power consumption results for 4 6 bit DCO circuits with one PMOS and NMOS PMOS switching network have also been presented.The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits.Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

Self-identification of electronically scanned signatures(ESS)and digitally constructed signatures(DCS)

The use of electronic signatures as a form of identification is increasingly common,yet they have been shown to lack the dynamic features found in online signatures.In this study,handwritten signatures were scanned to produce electronically scanned signatures(ESS)which were then digitally altered to produce digitally constructed signatures(DCS).The ESS and DCS were presented back to participants to identify which were genuine.Only 1%of participants correctly identified all signatures,with a mean score of 57.6%identifications.The lack of self-recognition of ESS raises questions on their reliability and usefulness as means of personal identification.

New directions of digitally driven S&T evaluation

Science and Technology(S&T)evaluation plays a baton role in developing science and technology innovation.However,traditional S&T evaluation indicators and methods are difficult to apply effectively in S&T evaluation practice.This paper analyzes the transformation of the S&T evaluation paradigm in the digital environment.Theories,methods,and tools of S&T evaluation research are continuously innovated and optimized;big data becomes the driving force of S&T evaluation development;the role played by S&T evaluation is shifting from a provider of statistical data and information to a participant in S&T decision-making activities.S&T evaluation research should focus on improving data retrieval and organization,knowledge mining and knowledge discovery,and intelligent evaluation models.Moreover,we suggest that scientists carry out S&T evaluation in agreement with the needs of S&T development:1)monitoring and sensing the development of science and technology in real-time with the help of emerging digital technologies;2)exploring solutions to major concerns such as technical project management mechanisms,utilizing advanced data science and digital technologies to identify important scientific frontiers,and leveraging big data in science of science to reveal patterns and characteristics of scientific structures and activities;3)carrying out problem-oriented evaluation research practice focused on four aspects,including intelligent project evaluation,evaluation of the critical technology competitiveness,talent assessment,and diagnostic evaluation of the research entity competitiveness.