Numerical simulation study of organic nonvolatile memory with polysilicon floating gate

A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated,in which polysilicon is sandwiched between oxide layers as a floating gate.Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed.The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing（P/E） operations at various P/E voltages are discussed.The simulated results show that present memory exhibits a large memory window of 57.5 V,and a high read current on/off ratio of ≈ 10~3.Compared with the reported experimental results,these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects,which shows great promise in device designing and practical application.

Combined effects of cycling endurance and total ionizing dose on floating gate memory cells

The combined effects of cycling endurance and radiation on floating gate memory cell are investigated in detail,and the obtained results are listed below.(i)The programmed flash cells with a prior appropriate number of program and easing cycling stress exhibit much smaller threshold voltage shift than without those in response to radiation,which is ascribed mainly to the recombination of trapped electrons(introduced by cycling stress)and trapped holes(introduced by irradiation)in the oxide surrounding the floating gate.(ii)The radiation induced transconductance degradation in prior cycled flash cell is more severe than those without cycling stress in the programmed state or erased state.(iii)Radiation is more likely to set up the interface generation in programmed state than in erased state.This paper will be useful in understanding the issues involved in cycling endurance and radiation effects as well as in designing radiation hardened floating gate memory cells.

Effects of post-annealed floating gate on the performance of AlGaN/GaN heterostructure field-effect transistors

AlGaN/GaN heterostructure field-effect transistors （HFETs） with different floating gate lengths and floating gates annealed at different temperatures, are fabricated. Using the measured capacitance-voltage curves of the gate Shottky contacts for the AlGaN/GaN HFETs, we find that after floating gate experiences 600℃ rapid thermal annealing, the larger the floating gate length, the larger the two-dimensional electron gas electron density under the gate region is. Based on the measured capacitance-voltage and current-voltage curves, the strain of the AlGaN barrier layer in the gate region is calculated, which proves that the increased electron density originates from the increased strain of the AlGaN barrier layer.

A novel enhancement mode AlGaN/GaN high electron mobility transistor with split floating gates

A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structure.The simulation results revealed that the V_（th） decreases with the increase of polarization sheet charge density and the tunnel dielectric（between FGs and AlGaN） thickness,while it increases with the increase of FGs sheet charge density and blocking dielectric（between FGs and control gate） thickness.In the case of the same gate length,the V_（th） will left shift with decreasing FG length.More interestingly,the split FGs could significantly reduce the device failure probability in comparison with the single large area FG structure.

Design,modelling,and simulation of a floating gate transistor with a novel security feature

This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,including scanning capacitance microscopy(SCM).The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate,even in nano-meter scales.The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate.This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic.Furthermore,this model was verified with a simulation.In addition,the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor.The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated.Finally,the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.

Van der Waals materials-based floating gate memory for neuromorphic computing

With the advent of the“Big Data Era”,improving data storage density and computation speed has become more and more urgent due to the rapid growth in different types of data.Flash memory with a floating gate(FG)structure is attracting great attention owing to its advantages of miniaturization,low power consumption and reli-able data storage,which is very effective in solving the problems of large data capacity and high integration density.Meanwhile,the FG memory with charge storage principle can simulate synaptic plasticity perfectly,breaking the traditional von Neumann computing ar-chitecture and can be used as an artificial synapse for neuromorphic computations inspired by the human brain.Among many candidate materials for manufacturing devices,van der Waals(vdW)materials have attracted widespread attention due to their atomic thickness,high mobility,and sustainable miniaturization properties.Owing to the arbitrary stacking ability,vdW heterostructure combines rich physics and potential 3D integration,opening up various possibilities for new functional integrated devices with low power consumption and flexible applications.This paper provides a comprehensive review of memory devices based on vdW materials with FG structure,including the working principles and typical structures of FG structure devices,with a focus on the introduction of various highperformance FG memories and their versatile applications in neuro-morphic computing.Finally,the challenges of neuromorphic devices based on FG structures are also discussed.This review will shed light on the design and fabrication of vdW material-based memory devices with FG engineering,helping to promote the development of practical and promising neuromorphic computing.

A fully on-chip fast-transient NMOS low dropout voltage regulator with quasi floating gate pass element

This paper presents a fully on-chip NMOS low-dropout regulator（LDO） for portable applications with quasi floating gate pass element and fast transient response.The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump,which allows the charge pump to be a small economical circuit with small silicon area.In addition,a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient.The proposed LDO has been implemented in a 0.35 μm BCD process.From experimental results,the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and Iq of 395 μA.Under full-range load current step,the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV,respectively.

Low voltage floating gate MOSFET based current differencing transconductance amplifier and its applications

This article presents a low voltage low power configuration of current differencing transconductance amplifier（CDTA）based on floating gate MOSFET.The proposed CDTA variant operates at lower supply voltage±1.4 V with total static power dissipation of 2.60 mW due to the low voltage feature of floating gate MOSFET.High transconductance up to 6.21 mA/V is achieved with extended linear range of the circuit i.e.±130μA.Two applications are illustrated to demonstrate the effectiveness of the proposed active block.A quadrature oscillator is realized using FGMOS based CDTA,two capacitors,and a resistor.The resistor is implemented using two NMOSFETs to provide high linearity and tunablility.Another application is the Schmitt trigger circuit based on the proposed CDTA variant.All circuits are simulated by using SPICE and TSMC 130 nm technology.

Analysis of 3D NAND technologies and comparison between charge-trap-based and floating-gate-based flash devices

NAND flash chips have been innovated from two-dimension （2D） design which is based on planar NAND cells to three-dimension （3D） design which is based on vertical NAND cells. Two types of NAND flash technologies-charge-trap （CT） and floating-gate （FG） are presented in this paper to introduce NAND flash designs in detail. The physical characteristics of CT-based and FG-based 3D NAND flashes are analyzed. Moreover, the advantages and disadvantages of these two technologies in architecture, manufacture, interference and reliability are studied and compared.

Temperature-controlled multisensory neuromorphic devices for artificial visual dynamic capture enhancement

Multi-sensory neuromorphic devices(MND)have broad potential in overcoming the structural bottleneck of von Neumann in the era of big data.However,the current multisensory artificial neuromorphic system is mainly based on unitary nonvolatile memory or volatile synaptic devices without intrinsic thermal sensitivity,which limits the range of biological multisensory perception and the flexibility and computational efficiency of the neural morphological computing system.Here,a temperature-dependent memory/synaptic hybrid artificial neuromorphic device based on floating gate phototransistors(FGT)is fabricated.The CsPbBr_(3)/TiO_(2)core–shell nanocrystals(NCs)prepared by in-situ pre-protection low-temperature solvothermal method were used as the photosensitive layer.The device exhibits remarkable multi-level visual memory with a large memory window of 59.6 V at room temperature.Surprisingly,when the temperature varies from 20 to 120℃back and forth,the device can switch between nonvolatile memory and volatile synaptic device with reconfigurable and reversible behaviors,which contributes to the efficient visual/thermal fusion perception.This work expands the sensory range of multisensory devices and promotes the development of memory and neuromorphic devices based on organic field-effect transistors(OFET).

Band-tailored van der Waals heterostructure for multilevel memory and artificial synapse

Two-dimensional(2D)van der Waals heterostructure(vdWH)-based floating gate devices show great potential for next-generation nonvolatile and multilevel data storage memory.However,high program voltage induced substantial energy consumption,which is one of the primary concerns,hinders their applications in lowenergy-consumption artificial synapses for neuromorphic computing.In this study,we demonstrate a three-terminal floating gate device based on the vdWH of tin disulfide(SnS2),hexagonal boron nitride(h-BN),and few-layer graphene.The large electron affinity of SnS2 facilitates a significant reduction in the program voltage of the device by lowering the hole-injection barrier across h-BN.Our floating gate device,as a nonvolatile multilevel electronic memory,exhibits large on/off current ratio(105),good retention(over 104 s),and robust endurance(over 1000 cycles).Moreover,it can function as an artificial synapse to emulate basic synaptic functions.Further,low energy consumption down to7 picojoule(pJ)can be achieved owing to the small program voltage.High linearity(<1)and conductance ratio(80)in long-term potentiation and depression(LTP/LTD)further contribute to the high pattern recognition accuracy(90%)in artificial neural network simulation.The proposed device with attentive band engineering can promote the future development of energy-efficient memory and neuromorphic devices.

A novel monolithic ultraviolet image sensor based on a standard CMOS process

We present a monolithic ultraviolet（UV） image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16×16 image sensor prototype chip is implemented in a 0.18μm standard CMOS logic process.The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/（mJ/cm^2） and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.

Ultrafast flash memory with large self-rectifying ratio based on atomically thin MoS_(2)-channel transistor

Flash memory with high operation speed and stable retention performance is in great demand to meet the requirements of big data.In addition,the realisation of ultrafast flash memory with novel functions offers a means of combining heterogeneous components into a homogeneous device without considering impedance matching.This report proposes a 20 ns programme flash memory with 10^(8) self-rectifying ratios based on a 0.65 nm-thick MoS_(2)-channel transistor.A high-quality van der Waals heterojunction with a sharp interface is formed between the Cr/Au metal floating layer and h-BN tunnelling layer.In addition,the large rectification ratio and low ideality factor(n=1.13)facilitate the application of the MoS_(2)-channel flash memory as a bit-line select transistor.Finally,owing to the ultralow MoS_(2)/h-BN heterojunction capacitance(50 fF),the memory device exhibits superior performance as a high-frequency(up to 1 MHz)sine signal rectifier.These results pave the way toward the potential utilisation of multifunctional memory devices in ultrafast two-dimensional NAND-flash applications.

Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS

With technology scaling,stability,power dissipation,and device variability,the impact of process,voltage and temperature(PVT)variations has become dominant for static random access memory(SRAM)analysis for productivity and failure.In this paper,ten-transistors(10T)and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors(FGMOS).Power centric parameters viz.read power,write power,hold power and delay are the performance analysis metrics.Further,the stochastic parameter variation to study the variability tolerance of the redesigned cell,PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell.Stability has been illustrated with the conventional butterfly method giving read static noise margin(RSNM)and write static noise margin(WSNM)metrics for read stability and write ability,respectively.A comparative analysis with standard six-transistor SRAM cell is carried out.HSPICE simulative analysis has been carried out for 32 nm technology node.The redesigned FGMOS SRAM cells provide improved performance.Also,these are robust and reliability efficient with comparable stability.