Model-Free Adaptive Frequency Calibration for Voltage-Controlled Oscillators

The operating frequency accuracy of the local oscillators is critical for the overall system performance in the communication systems.However,the high-precision oscillators could be too expensive for civil applications.In this paper,we propose a model-free adaptive frequency calibration framework for a voltage-controlled crystal oscillator(VCO)equipped with a time to digital converter(TDC),which can significantly improve the frequency accuracy of the VCO thus calibrated.The idea is to utilize a high-precision TDC to directly measure the VCO period which is then passed to a model-free method for working frequency calibration.One advantage of this method is that the working frequency calibration employs the system history of input/output(I/O)data,instead of establishing an accurate VCO voltagecontrolled oscillator model.Another advantage is the lightweight calibration method with low complexity such that it can be implemented on an MCU with limited computation capabilities.Experimental results show that the proposed calibration method can improve the frequency accuracy of a VCO from±20 ppm to±10 ppb,which indicates the promise of the modelfree adaptive frequency calibrator for VCOs.

2.7-4.0 GHz PLL with dual-mode auto frequency calibration for navigation system on chip

A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2.

A fast lock frequency synthesizer using an improved adaptive frequency calibration

An improved adaptive frequency calibration（AFC） has been employed to implement a fast lock phaselocked loop based frequency synthesizer in a 0.18μm CMOS process.The AFC can work in two modes：the frequency calibration mode and the store/load mode.In the frequency calibration mode,a novel frequency-detector is used to reduce the frequency calibration time to 16 us typically.In the store/load mode,the AFC makes the voltage-controlled oscillator（VCO） return to the calibrated frequency in about 1μs by loading the calibration result stored after the frequency calibration.The experimental results show that the VCO tuning frequency range is about 620-920 MHz and the in-band phase noise within the loop bandwidth of 10 kHz is-82 dBc/Hz.The lock time is about 20μs in frequency calibration mode and about 5 us in store/load mode.The synthesizer consumes 12 mA from a single 1.8 V supply voltage when steady.

A wide range sigma-delta fractional-N frequency synthesizer with adaptive frequency calibration

A wide range fractional-N frequency synthesizer in 0.18μm RF CMOS technology is implemented. A switched-capacitors bank LC-tank VCO and an adaptive frequency calibration technique are used to expand the frequency range.A 16-bit third-order sigma-delta modulator with dither is used to randomize the fractional spur. The active area is 0.6 mm;.The experimental results show the proposed frequency synthesizer consumes 4.3 raA from a single 1.8 V supply voltage except for buffers.The frequency range is 1.44-2.11 GHz and the frequency resolution is less than 0.4 kHz.The phase noise is -94 dBc/Hz @ 100 kHz and -121 dBc/Hz @ 1 MHz at the output of the prescaler with a loop bandwidth of approximately 120 kHz.The performance meets the requirements for the multi-band and multi-mode transceiver applications.

A low-noise widely tunable Gm-C filter with frequency calibration

A fourth-order Gm-C Chebyshev low-pass filter is presented as channel selection filter for reconfigurable multi-mode wireless receivers. Low-noise technologies are proposed in optimizing the noise characteristics of both the Gm cells and the filter topology. A frequency tuning strategy is used by tuning both the transconductance of the Gm cells and the capacitance of the capacitor banks. To achieve accurate cut-off frequencies, an on-chip calibration circuit is presented to compensate for the frequency inaccuracy introduced by process variation. The filter is fabricated in a 0.13 m CMOS process. It exhibits a wide programmable bandwidth from 322.5 k Hz to20 MHz. Measured results show that the filter has low input referred noise of 5.9 n V/（Hz）^（1/2） and high out-of-band IIP3 of 16.2 d Bm. It consumes 4.2 and 9.5 m W from a 1 V power supply at its lowest and highest cut-off frequencies respectively.

A Σ-Δ Fractional-N PLL Frequency Synthesizer with AFC for SRD Applications

A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.

A 5-GHz frequency synthesizer with constant bandwidth for low IF ZigBee transceiver applications

A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator（VCO）are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature（IQ）signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency（RF） complementary metal oxide semiconductor transistor （CMOS）technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.

Upgrade of the magnetic diagnostic system for restart of HT-6M operation

The HT-6M tokamak at the Thailand Institute of Nuclear Technology has been restarted.In order to ensure the smooth breakdown of plasma and obtain plasma discharge parameters,optimization of the poloidal field coils and upgrade of the magnetic diagnostics are described in this article.A perfect null field(stray field in the main chamber<10 G)is obtained using an ohmic heating field.To obtain important information about the plasma,an external magnetic diagnostics system is designed and calibrated,including a Rogowski coil(measuring plasma current),a magnetic probe(measuring external field),diamagnetic loops(measuringβ_(p))and so on.In order to realize high-frequency signal measurement and transmission,a series of frequency responses with the magnetic probe and transmission line are tested.Later,to verify the null field,a fitting code is developed to reconstruct the stray field in the vacuum chamber based on magnetic probe measurements and flux loops.The results show that the error is within 1.5%.This indicates the accuracy of the magnetic measurement system and ensures the preparation for the breakdown of plasma.

Review of satellite disciplined clock system

Satellite disciplined clock system(SDCS)composed of satellite timing receiver and local frequency synthesis is widely applied for its high accuracy and low cost.This paper provides a review of SDCS.Key technologies such as phase difference measurement,pulse noise process and frequency calibration are surveyed in detail.Disciplined clock model based on PI controller is built and disciplined process is analyzed.The methods of realizing the disciplined clock circuit are classified and summarized.A prototype based on FPGA is proposed.At last development trend of SDCS is discussed.

A multi-standard active-RC filter with accurate tuning system

A low-power, highly linear, multi-standard, active-RC filter with an accurate and novel tuning architecture is presented. It exhibits IEEE 802.11 a/b/g （9.5 MHz） and DVB-H （3 MHz, 4 MHz） application. The filter exploits digitally-controlled polysilicon resistor banks and a phase lock loop type automatic tuning system. The novel and complex automatic frequency calibration scheme provides better than 4 corner frequency accuracy, and it can be powered down after calibration to save power and avoid digital signal interference. The filter achieves OIP3 of 26 dBm and the measured group delay variation of the receiver filter is 50 ns （WLAN mode）. Its dissipation is 3.4 mA in RX mode and 2.3 mA （only for one path） in TX mode from a 2.85 V supply. The dissipation of calibration consumes 2 mA. The circuit has been fabricated in a 0.35μm 47 GHz SiGe BiCMOS technology; the receiver and transmitter filter occupy 0.21 mm^2 and 0.11 mm^2 （calibration circuit excluded）, respectively.

A 2.5-V 56-mW baseband chain in a multistandard TV tuner for mobile and multimedia applications

This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain,and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz.The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps.Design trade-offs are carefully considered in designing the baseband circuit,and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%.A DC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing,and the remaining offset voltage is only 1.87 mV.Implemented in a 0.13-μm SiGe technology with a 0.6-mm2 die size,this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.

A 3.96 GHz phase-locked loop for mode-1 MB-OFDM UWB hopping carrier generation

A fully integrated phase-locked loop（PLL） is presented for a single quadrature output frequency of 3.96 GHz.The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation.An adaptive frequency calibration loop is incorporated into the PLL.The capacitance area in the loop filter is largely reduced through a capacitor multiplier.Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die area.Measurement results show that the PLL achieves a phase noise of-70 dBc/Hz at 10 kHz offset and-113 dBc/Hz at 1 MHz offset.The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps.The reference spur level is less than-68 dBc.

A low power high linearity baseband for a direct conversation CMMB tuner

An analog baseband circuit made in a 0.35-μm SiGe BiCMOS process is presented for China Multi-media Mobile Broadcasting（CMMB） direct conversion receivers.A high linearity 8th-order Chebyshev low pass filter（LPF） with accurate calibration system is used.Measurement results show that the filter provides 0.5-dB pass-band ripple,4% bandwidth accuracy,and-35-dB attenuation at 6 MHz with a cutoff frequency of 4 MHz.The current steering type variable gain amplifier（VGA） achieves more than 40-dB gain range with excellent temperature compensation.This tuner baseband achieves an OIP3 of 25.5 dBm,dissipates 16.4 mA under a 2.8-V supply and occupies 1.1 mm^2 of die size.