CMOS Automatic Gain Control Circuit with DC Offset Cancellation for FM/cw Ladar

This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 gm standard CMOS process. Simulation and measurement results verified that its gain ranged from -20 dB to 30 dB, and band- width ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.

Single-Stage Wide-Range CMOS VGA with Temperature Compensation and Linear-in-dB Gain Control

A novel wide-range CMOS variable gain amplifier （VGA） topology is presented. The proposed VGA is composed of a variable transconductor and a novel variable output resistor and can offer a high gain variation range of 80dB while using a single variable-gain stage. Temperature-compensation and decibel-linear gain characteristic are achieved by using a control circuit that provides a gain error lower than ±1.5dB over the full temperature and gain ranges. Realized in 0.25μm CMOS technology, a prototype of the proposed VGA provides a total gain range of 64.5dB with 55.6dB-linear range,a P-1dB varying from - 17.5 to 11.5dBm,and a 3dB-bandwith varying from 65 to 860MHz while dissipating 16.5mW from a 2.5V supply voltage.

Design and implementation of digital closed-loop drive control system of a MEMS gyroscope

In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop （PLL） in frequency control and an automatic gain control （AGC） method in amplitude control. A digital processing circuit with a field programmable gate array （FPGA） is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.

Modeling of a Multiple Digital Automatic Gain Control System

Automatic gain control （AGC） has been used in many applications. The key features of AGC, including a steady state output and static/dynamic timing response, depend mainly on key parameters such as the reference and the filter coefficients. A simple model developed to describe AGC systems based on several simple assumptions shows that AGC always converges to the reference and that the timing constant depends on the filter coefficients. Measures are given to prevent oscillations and limit cycle effects. The simple AGC system is adapted to a multiple AGC system for a TV tuner in a much more efficient model. Simulations using the C language are 16 times faster than those with MATLAB, and 10 times faster than those with a mixed register transfer level （RTL）-simulation program with integrated circuit emphasis （SPICE） model.

A digitally calibrated CMOS RMS power detector for RF automatic gain control

This paper presents the design and implementation of a digitally calibrated CMOS wideband radio frequency(RF) root-mean-square(RMS) power detector for high accuracy RF automatic gain control(AGC).The proposed RMS power detector demonstrates accurate power detection in the presence of process,supply voltage, and temperature(PVT) variations by employing a digital calibration scheme.It also consumes low power and occupies a small chip area.The measurement results show that the scheme improves the accuracy of the detector to better than 0.3 dB over the PVT variations and wide operating frequency range from 0.2 to 0.8 GHz.Implemented in a 0.18μm CMOS process and occupying a small die area of 263×214μm^2,the proposed digitally calibrated CMOS RMS power detector only consumes 1.6 mA in power detection mode and 2.1 mA in digital calibration mode from a 1.8 V supply voltage.

A differential automatic gain control circuit with two-stage -10 to 50 dB tuning range VGAs

A differential automatic gain control （AGC） circuit is presented. The AGC architecture contains twostage variable gain amplifiers （VGAs） which are implemented with a Gilbert cell, a peak detector （PD）, a low pass filter, an operational amplifier, and two voltage to current （V-I） convertors. One stage VGA achieves 30 dB gain due to the use of active load. The AGC circuit is implemented in UMC 0.18-um single-poly six-metal CMOS process technology. Measurement results show that the final differential output swing of the 2nd stage VGA is about 0.9-Vpp; the total gain of the two VGAs can be varied linearly from -10 to 50 dB when the control voltage varies from 0.3 to 0.9 V. The final circuit （containing output buffers and a band-gap reference） consumes 37 mA from single 1.8 V voltage supply. For a 50 mV amplitude 60% modulation depth input AM signal it needs 100 us to stabilize the output. The frequency response of the circuit has almost a constant -3 dB bandwidth of 2.2 MHz. Its OIP3 result is at 19 dBm.

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What＇s more, a novel DC offset cancellation （DCOC） circuit with an HPCF （high pass cutoff frequency） less than 10 kHz is proposed. The AGC is fabricated by a 0.18μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ×300μm2.

An output amplitude configurable wideband automatic gain control with high gain step accuracy

An output amplitude configurable wideband automatic gain control（AGC） with high gain step accuracy for the GNSS receiver is presented.The amplitude of an AGC is configurable in order to cooperate with baseband chips to achieve interference suppression and be compatible with different full range ADCs.And what’s more,the gain-boosting technology is introduced and the circuit is improved to increase the step accuracy.A zero,which is composed by the source feedback resistance and the source capacity,is introduced to compensate for the pole.The AGC is fabricated in a 0.18μm CMOS process.The AGC shows a 62 dB gain control range by 1 dB each step with a gain error of less than 0.2 dB.The AGC provides 3 dB bandwidth larger than 80 MHz and the overall power consumption is less than 1.8 mA,and the die area is 800 x 300μm^2.

A low power automatic gain control loop for a receiver

This paper proposes a new structure to lower the power consumption of a variable gain amplifier（VGA） and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying（ASK） based IF-stage.It includes an automatic gain control（AGC） loop and ASK demodulator.The AGC mainly consists of sixstage VGAs.The IF-stage is realized in 0.18μm CMOS technology.The measurement results show that the power consumption of the whole system is very low.The system consumes 730μA while operating at 1.8 V.The minimum ASK signal the system could detect is 0.7 mV（peak to peak amplitude）.

Response characteristics of sonar receiver under intense sound pulse

For anti-jamming and anti-countermeasure techniques of the sonar receiver, the response characteristics of the automatic gain control （AGC） circuit and the survivability of the prime circuit under strong interference are analyzed by simulations and experiments. An AGC simulation model based on the voltage control amplifier VCA810 prototype is proposed. Then static and dynamic simulations are realized with single frequency signal and linear frequency modulated （LFM） signal commonly used in the active sonar. Based on intense sound pulse （ISP） interference experiments, the real-time response characteristics of each module of the receiver are studied to verify the correctness of the model as well as the simulation results. Simulation and experiment results show that, under 252 dB/20 μs ISP interference, the specific sonar receiver will produce sustained cut top oscillation above 30 ms, which may affect the receiver and block the regular sonar signal.

Design of a 6.25 Gbps backplane SerDes with adaptive decision feedback equalization

A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference （ISI）, the core employed a half-rate four-tap decision feedback equalizer （DFE）. The equalizer used the Signsign least mean-squared （SS-LMS） algorithm to realize the coefficient adaptation. An automatic gain control （AGC） amplifier with the sign least mean-squared （S-LMS） algorithm has been used to compensate the transmission media loss. To recover the clock signal from the input data serial and provide for the DFE and AGC, a bang-bang clock recovery （BB-CR） is adopted. A third order phase loop loek （PLL） model was proposed to predict characteristics of the BB-CR. The core has been verified by behavioral modeling in MATLAB. The results indicate that the core can meet the specifications of the backplane receiver. The DFE recovered data over a 34＂ FR-4 backplane has a peak-to-peak jitter of 17 ps, a horizontal eye opening of 0.87 UI, and a vertical eye opening of 500 mVpp.

Linear-in-dB Variable-Gain Downconversion Mixer for Zero Intermediate Frequency Receivers

In-phase/quadrature （I/Q） mismatch is a key problem in zero intermediate frequency （ZIF） receiver architectures. Although integration and careful layout can alleviate I/Q mismatch, circuit and system level calibrations are also needed due to process variations and variable operating conditions. The amplitude im- balance between I/Q channels was calibrated using a modified R-2R ladder to achieve fine linear-in-dB variable gain. A downconversion mixer working in the 2,4-GHz band was developed for a wireless local area network （WLAN） ZIF receiver using 0.25μm complementary metal-oxide semiconductor （CMOS）. The twostage mixer configuration relaxes the tradeoff between noise and linearity. Experimental results verify the fine linear-in-dB variable conversion gain of the mixer, which can also be used as part of an automatic gain control （AGC）loop.

Dual-band RF receiver for GPS-L1 and compass-B1 in a 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control （AGC） loop is utilized to improve the receiver＇s robustness by optimizing the conversion gain of the analog-to-digital converter （ADC）. While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure （NF） of about 1.8 dB, an image rejection （IMR） of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about -36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.

A high-performance low-power CMOS AGC for GPS application

A wide tuning range,low power CMOS automatic gain control（AGC） with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier（VGA）,a comparator and a charge pump,and the dB-linear gain is controlled by the charge pump.The AGC was implemented in a 0.18μm CMOS technology.The dynamic range of the VGA is more than 55 dB,the bandwidth is 30 MHz,and the gain error is lower than±1.5 dB over the full temperature and gain ranges.It is designed for GPS application and is fed from a single 1.8 V power supply. The AGC power consumption is less than 5 mW,and the area of the AGC is 700×450μm^2.

A SiGe BiCMOS multi-band tuner for mobile TV applications

This paper presents the circuit design and measured performance of a multi-band tuner for mobile TV applications. The tuner RFIC is composed of a wideband front-end, an analog baseband, a full integrated fractional- N synthesizer and an Iac digital interface. To meet the stringent adjacent channel rejection （ACR） requirements of mobile TV standards while keeping low power consumption and low cost, direct conversion architecture with a local AGC scheme is adopted in this design. Eighth-order elliptic active-RC filters with large stop band attenuation and a sharp transition band are chosen as the channel select filter to further improve the ACR preference. The chip is fabricated in a 0.35-#m SiGe BiCMOS technology and occupies a silicon area of 5.5 mm2. It draws 50 mA current from a 3.0 V power supply. In CMMB application, it achieves a sensitivity of-97 dBm with 1/2 coding QPSK signal input and over 40 dB ACR.