In this work,a surface-potential based compact model focusing on the quantum confinement effects of ultimately scaled gate-all-around(GAA)MOSFET is presented.Energy quantization with sub-band formation along the radiu...In this work,a surface-potential based compact model focusing on the quantum confinement effects of ultimately scaled gate-all-around(GAA)MOSFET is presented.Energy quantization with sub-band formation along the radius direction of cylindrical GAAs or thickness direction of nanosheet GAAs leads to significant quantization effects.An analytical model of surface potentials is developed by solving the Poisson equation with incorporating sub-band effects.In combination with the existing transport model framework,charge-voltage and current-voltage formulations are developed based on the surface potential.The model formulations are then extensively validated using TCAD numerical simulations as well as Si data of nanosheet GAA MOSFETs.Simulations of typical circuits verify the model robustness and convergence for its applications in GAA technology.展开更多
Using capacitance,conductance and noise measurements,we investigate the trapping behavior at the surface and in the core of triangular-shaped one-dimensional (1 D) array of GaN nanowire gate-all-around field effect tr...Using capacitance,conductance and noise measurements,we investigate the trapping behavior at the surface and in the core of triangular-shaped one-dimensional (1 D) array of GaN nanowire gate-all-around field effect transistor (GAA FET),fabricated via a top-down process.The surface traps in such a low dimensional device play a crucial role in determining the device performance.The estimated surface trap density rapidly decreases with increasing frequency,ranging from 6.07 × 1012 cm-2·eV-1 at 1 kHz to 1.90 × 1011 cm-2·eV-1 at 1 MHz,respectively.The noise results reveal that the power spectral density increases with gate voltage and clearly exhibits 1/f-noise signature in the accumulation region (Vgs > Vth =3.4 V) for all frquencies.In the surface depletion region (1.5 V < Vgs < Vth),the device is governed by 1/fat lower frequencies and 1/f2 noise at frequencies higher than ~ 5 kHz.The 1/f2 noise characteristics is attributed to additional generation-recombination (G-R),mostly caused by the electron trapping/detrapping process through deep traps located in the surface depletion region of the nanowire.The cutoff frequency for the 1/f2 noise characteristics further shifts to lower frequency of 102-103 Hz when the device operates in deep-subthreshold region (Vgs < 1.5 V).In this regime,the electron trapping/detrapping process through deep traps expands into the totally depleted nanowire core and the G-R noise prevails in the entire nanowire channel.展开更多
For the development of ultra-sensitive electrical bio/chemical sensors based on nanowire field effect transistors （FETs）, the influence of the ions in the solution on the electron transport has to be understood. For...For the development of ultra-sensitive electrical bio/chemical sensors based on nanowire field effect transistors （FETs）, the influence of the ions in the solution on the electron transport has to be understood. For this purpose we establish a simulation platform for nanowire FETs in the liquid environment by implementing the modified Poisson-Boltzmann model into Landauer transport theory. We investigate the changes of the electric potential and the transport characteristics due to the ions. The reduction of sensitivity of the sensors due to the screening effect from the electrolyte could be successfully reproduced. We also fabricated silicon nanowire Schottky-barrier FETs and our model could capture the observed reduction of the current with increasing ionic concentration. This shows that our simulation platform can be used to interpret ongoing experiments, to design nanowire FETs, and it also gives insight into controversial issues such as whether ions in the buffer solution affect the transport characteristics or not.展开更多
We explore 10-nm wide Si nanowire （SiNW） field-effect transistors （FETs） for logic applications, via the fabrication and testing of SiNW-based ring oscillators. We report on SiNW surface treatments and dielectric ...We explore 10-nm wide Si nanowire （SiNW） field-effect transistors （FETs） for logic applications, via the fabrication and testing of SiNW-based ring oscillators. We report on SiNW surface treatments and dielectric annealing, for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio （-10s）, low drain-induced barrier lowering （-30 mV） and low subthreshold swing （-80 mV/decade）. The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs are also explored. The inverter demonstrates the highest voltage gain （-148） reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications.展开更多
基金supported in part by the Natural Science Foundation of China(62125401 and 62074006)the major scientific instruments and equipments development grant(61927901)the Shenzhen Fundamental Research Program(GXWD20200827114656001).
文摘In this work,a surface-potential based compact model focusing on the quantum confinement effects of ultimately scaled gate-all-around(GAA)MOSFET is presented.Energy quantization with sub-band formation along the radius direction of cylindrical GAAs or thickness direction of nanosheet GAAs leads to significant quantization effects.An analytical model of surface potentials is developed by solving the Poisson equation with incorporating sub-band effects.In combination with the existing transport model framework,charge-voltage and current-voltage formulations are developed based on the surface potential.The model formulations are then extensively validated using TCAD numerical simulations as well as Si data of nanosheet GAA MOSFETs.Simulations of typical circuits verify the model robustness and convergence for its applications in GAA technology.
文摘Using capacitance,conductance and noise measurements,we investigate the trapping behavior at the surface and in the core of triangular-shaped one-dimensional (1 D) array of GaN nanowire gate-all-around field effect transistor (GAA FET),fabricated via a top-down process.The surface traps in such a low dimensional device play a crucial role in determining the device performance.The estimated surface trap density rapidly decreases with increasing frequency,ranging from 6.07 × 1012 cm-2·eV-1 at 1 kHz to 1.90 × 1011 cm-2·eV-1 at 1 MHz,respectively.The noise results reveal that the power spectral density increases with gate voltage and clearly exhibits 1/f-noise signature in the accumulation region (Vgs > Vth =3.4 V) for all frquencies.In the surface depletion region (1.5 V < Vgs < Vth),the device is governed by 1/fat lower frequencies and 1/f2 noise at frequencies higher than ~ 5 kHz.The 1/f2 noise characteristics is attributed to additional generation-recombination (G-R),mostly caused by the electron trapping/detrapping process through deep traps located in the surface depletion region of the nanowire.The cutoff frequency for the 1/f2 noise characteristics further shifts to lower frequency of 102-103 Hz when the device operates in deep-subthreshold region (Vgs < 1.5 V).In this regime,the electron trapping/detrapping process through deep traps expands into the totally depleted nanowire core and the G-R noise prevails in the entire nanowire channel.
文摘For the development of ultra-sensitive electrical bio/chemical sensors based on nanowire field effect transistors （FETs）, the influence of the ions in the solution on the electron transport has to be understood. For this purpose we establish a simulation platform for nanowire FETs in the liquid environment by implementing the modified Poisson-Boltzmann model into Landauer transport theory. We investigate the changes of the electric potential and the transport characteristics due to the ions. The reduction of sensitivity of the sensors due to the screening effect from the electrolyte could be successfully reproduced. We also fabricated silicon nanowire Schottky-barrier FETs and our model could capture the observed reduction of the current with increasing ionic concentration. This shows that our simulation platform can be used to interpret ongoing experiments, to design nanowire FETs, and it also gives insight into controversial issues such as whether ions in the buffer solution affect the transport characteristics or not.
基金The authors acknowledge H. Ahmad and Y. -S. Shin for graphics assistance. This work was funded by the National Science Foundation under Grant CCF-0541461 and the Department of Energy （DE-FG02-04ER46175）. D. Tham gratefully acknowledges support by the KAUST Scholar Award.
文摘We explore 10-nm wide Si nanowire （SiNW） field-effect transistors （FETs） for logic applications, via the fabrication and testing of SiNW-based ring oscillators. We report on SiNW surface treatments and dielectric annealing, for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio （-10s）, low drain-induced barrier lowering （-30 mV） and low subthreshold swing （-80 mV/decade）. The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs are also explored. The inverter demonstrates the highest voltage gain （-148） reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications.
