A review on the design of ternary logic circuits

A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

A weighted averaging method for signal probability of logic circuit combined with reconvergent fan-out structures

By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed.Considering the failure probability of the gate,first,the first reconvergent fan-ins corresponding to the reconvergent fan-outs were identified to locate the important signal correlation nodes based on the principle of homologous signal convergence.Secondly,the reconvergent fan-in nodes of the multiple reconverging structure in the circuit were identified by the sensitization path to determine the interference sources to the signal probability calculation.Then,the weighted signal probability was calculated by combining the weighted average approach to correct the signal probability.Finally,the reconvergent fan-out was quantified by the mixed-calculation strategy of signal probability to reduce the impact of multiple reconvergent fan-outs on the accuracy.Simulation results on ISCAS85 benchmarks circuits show that the proposed method has approximate linear time-space consumption with the increase in the number of the gate,and its accuracy is 4.2%higher than that of the IWAA.

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

A Comparative Study of Majority/Minority Logic Circuit Synthesis Methods for Post-CMOS Nanotechnologies

The physical limitations of complementary metal-oxide semiconductor?(CMOS) technology have led many researchers to consider other alternative technologies. Quantum-dot cellular automate (QCA), single electron tunneling (SET), tunneling phase logic (TPL), spintronic devices, etc., are some of the nanotechnologies that are being considered as possible replacements for CMOS. In these nanotechnologies, the basic logic units used to implement circuits are majority and/or minority gates. Several majority/minority logic circuit synthesis methods have been proposed. In this paper, we give a comparative study of the existing majority/minority logic circuit synthesis methods that are capable of synthesizing multi-input multi-output Boolean functions. Each of these methods is discussed in detail. The optimization priorities given to different factors such as gates, levels, inverters, etc., vary with technologies. Based on these optimization factors, the results obtained from different synthesis methods are compared. The paper also analyzes the optimization capabilities of different methods and discusses directions for future research in the synthesis of majority/minority logic networks.

A Novel High-Performance Lekage-Tolerant, Wide Fan-In Domino Logic Circuit in Deep-Submicron Technology

As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design for low power consumption, faster circuit speed and high performance. Due to wide fan-in domino logic, its logic gate suffer from noise sensitivity, if we improve sensitivity, sub-threshold and gate oxide leakage current dominate in evaluation network, which increases the power consumption and reduces the performance of the circuit. The proposed circuit improves the dynamic power consumption and reduces the delay which improves the speed of the circuit. Simulation is performed in BISM4 Cadence environment at 65 nm process technology, with supply voltage 1 V at 100 MHz frequency and bottleneck operating temperature of 27°C with CL = 1 fF. From the result average power improvement by proposed circuit 1 & 2 for 8 input OR gate is 10.1%, 15.28% SFLD, 48.56%, 51.49% CKD, 55.17%, 57.71% HSD and improvement of delay is 1.10%, 12.76% SFLD, 19.13%, 28.63% CKD, 4.32%, 15.59% HSD, 19.138%, 44.25% DFD respectively.

Two Analytical Methods for Detection and Elimination of the Static Hazard in Combinational Logic Circuits

In this paper, the authors continue the researches described in [1], that consists in a comparative study of two methods to eliminate the static hazard from logical functions, by using the form of Product of Sums (POS), static hazard “0”. In the first method, it used the consensus theorem to determine the cover term that is equal with the product of the two residual implicants, and in the second method it resolved a Boolean equation system. The authors observed that in the second method the digital hazard can be earlier detected. If the Boolean equation system is incompatible (doesn’t have solutions), the considered logical function doesn’t have the static 1 hazard regarding the coupled variable. Using the logical computations, this method permits to determine the needed transitions to eliminate the digital hazard.

Tribotronic triggers and sequential logic circuits

In this paper, a floating-gate tribotronic transistor （FGTT） based on a mobile triboelectric layer and a traditional silicon-based field-effect transistor （FET） is proposed. In the FGTT, the triboelectric charges in the layer created by contact electrification can be used to modulate charge carrier transport in the transistor. Based on the FGTTs and FETs, a tribotronic negated AND （NAND） gate that achieves mechanical-electrical coupled inputs, logic operations, and electrical level outputs is fabricated. By further integrating tribotronic NAND gates with traditional digital circuits, several basic units such as the tribotronic S-R trigger, D trigger, and T trigger have been demonstrated. Additionally, tribotronic sequential logic circuits such as registers and counters have also been integrated to enable external contact triggered storage and computation. In contrast to the conventional sequential logic units controlled by electrical signals, contact-triggered tribotronic sequential logic circuits are able to realize direct interaction and integration with the external environment. This development can lead to their potential application in micro/nano-sensors, electromechanical storage, interactive control, and intelligent instrumentation.

On the operating speed and energy efficiency of GaN-based monolithic complementary logic circuits for integrated power conversion systems

Gallium nitride(GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules.Recently emerging GaN-based p-channel field-effect transistors(FETs)and monolithic integration techniques enable the implementation of GaN-based complementary logic(CL)circuits and thereby offer an additional pathway to improving the system-level energy efficiency and functional-ity.In this article,holistic analyses are conducted to evaluate the potential benefits of introducing GaN CL circuits into the integrated power systems,based on the material limit of GaN and state-of-the-art experimental results.It is revealed that the propagation delay of a single-stage CL gate based on the commercial p-GaN gate power HEMT(high-electron-mobility transistor)platform could be as short as sub-nanosecond,which sufficiently satis-fies the requirement of power conversion systems typically with operating frequencies less than 10 MHz.With the currently adopted n-FET-based logic gates(e.g.,directly coupled FET logic)replaced by CL gates,the power consumption of peripheral logic circuits could be substantially suppressed by more than 10^(3) times,mainly due to the elimination of the pronounced static power loss.Consequently,the energy efficiency of the entire system could be substantially improved.

A novel circuit design for complementary resistive switch-based stateful logic operations

Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch（CRS）-based stateful logic operations. The proposed circuit can automatically write the destructive CRS cells back to the original states. In addition, the circuit can be used in massive passive crossbar arrays which can reduce sneak path current greatly. Moreover, the steps for CRS logic operations using our proposed circuit are reduced compared with previous circuit designs. We validate the effectiveness of our scheme through Hspice simulations on the logic circuits.

An approach to predicting dynamic power dissipation of coupled interconnect network in dynamic CMOS logic circuits

In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relation to the signal on that node, and it also depends on signals on its neighbor nodes through coupling capacitors. Thus, for their limitation in dealing with ca-pacitively coupled nets, past jobs on power estimation are facing rigorous challenges and need to be ameliorated. This paper proposes and proves a simple and fast approach to predicting dynamic power dissipation of coupled interconnect networks: a coupling capacitor in dynamic CMOS logic circuits is decoupled and mapped into an equivalent cell containing an XOR gate and a grounded capacitor, and the whole circuit after mapping, consuming the same power as the original one, could be easily managed by generally-used gate-level power estimation tools. This paper also investigates the correlation coefficient method (CCM). Given the signal probabilities and the correlation coefficients between signals, the dynamic power of interconnect networks can be calculated by using CCM. It can be proved that the decoupling method and CCM draw identical results, that is to say, the decoupling method implicitly preserves correlation properties between signals and there is no accuracy loss in the decoupling process. Moreover, it is addressed that the coupling capacitors in static CMOS circuits could be decoupled and mapped into an equivalent cell containing a more complicated logic block, and the power can be obtained by the probability method for dynamic CMOS logic circuits.

OPTIMIZATION OF MULTIPLE-OUTPUT EXCLUSIVE-OR LOGIC CIRCUITS

A method is presented for optimizing multiple-output exclusive-OR logic circuits. The effect of common gates on the optimization of logic circuits is studied. The concepts of common function, residue function and remainder term are introduced. A computer method for searching the optimum polarity is proposed. This method can be used to design the logic circuit which needs the minimum number of exclusive-OR gates.

Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods.

Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits

This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.

基于Logic Converter的组合逻辑电路设计

介绍了虚拟仪器Logic Converter的主要特点和使用方法 ,并以典型组合逻辑电路进行分析。实例表明,基于Logic Converter的组合逻辑电路设计不仅方便、简洁,而且大大提高了学生的学习兴趣,巩固了课程教学效果。

Design and Implementation of Efficient Reversible Arithmetic and Logic Unit

In computing architecture, ALU plays a major role. Many promising applications are possible with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of these microcontrollers can be improved by applying Reversible Logic and Vedic Mathematics. In this paper, an efficient reversible Arithmetic and Logic Unit with reversible Vedic Multiplier is proposed and the simulation results show its effectiveness in reducing quantum cost, number of gates, and the total number of logical calculations.

ON EQUIVALENCE BETWEEN THE SEQUENTIAL CIRCUITS IN SERIES AND IN PARALLEL

Propose the sequential circuits with the ternary D-ffs in series^1. Discuss the equivalence between the sequential circuits with the p-valued flip-flops in series and in parallel as a part of studying the multiple valued logic circuits.

THE RESEARCH ON TERNARY TTL SCHMITT CIRCUITS

By analyzing the threshold-jumping of Schmitt circuits, this paper indicates that the core element realizing this function in binary TTL Schmitt circuits is the differential current switch with controllable threshold. Based on the characteristic having two kinds of signal-detection threshold in ternary TTL circuits, a ternary TTL Schmitt circuit having twice reactions of threshold-jumping is designed. The simulation with PSPICE proves that the designed circuit has ideal function of Schmitt circuits.

DESIGN OF TERNARY CURRENT-MODE CMOS CIRCUITS BASED ON SWITCH-SIGNAL THEORY

By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is suitable to current-mode CMOS circuits is proposed. Thecircuits, such as ternary full-adder etc., designed by using this theory have simpler circuit struc-tures and correct logic functions. It is confirmed that this theory is efficient in guiding the logicdesign of current-mode CMOS circuits at switch level.

THE NEW SUPER-HIGH-SPEED DIGITAL CIRCUIT BASED ON LINEAR AND-OR GATES

The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.

SIMPLIFICATION OF CURRENT-MODE MULTIVALUED CMOS CIRCUITS

This paper proposes a simplification method for realization of current-mode multivalued CMOS circuits. The key of this method is to find a cover on the K-map for a given multivalued function, which fits to the realization of current-mode CMOS circuits. The design example shows that the design presented in this paper is better than the design proposed by G. W. Dueck et al. (1987).