GROUP VELOCITY CONTROL SCHEME WITH LOW DISSIPATION

In order to prevent smearing the discontinuity, a modified term is added to the third order Upwind Compact Difference scheme to lower the dissipation error. Moreover, the dispersion error is controled to hold back the non physical oscillation by means of the group velocity control. The scheme is used to simulate the interactions of shock density stratified interface and the disturbed interface developing to vortex rollers. Numerical results are satisfactory.

A High Resolution Low Dissipation Hybrid Scheme for Compressible Flows

In this paper, an efficient hybrid shock capturing scheme is proposed to obtain accurate results both in the smooth region and around discontinuities for compressible flows. The hybrid algorithm is based on a fifth-order weighted essentially non-oscillatory （WENO） scheme in the finite volume form to solve the smooth part of the flow field, which is coupled with a characteristic-based monotone upstream-centered scheme for conservation laws （MUSCL） to capture discontinuities. The hybrid scheme is intended to combine high resolution of MUSCL scheme and low dissipation of WENO scheme. The two ingredients in this hybrid scheme are switched with an indicator. Three typical indicators are chosen and compared. MUSCL and WENO are both shock capturing schemes making the choice of the indicator parameter less crucial. Several test cases are carried out to investigate hybrid scheme with different indicators in terms of accuracy and efficiency. Numerical results demonstrate that the hybrid scheme in the present work performs well in a broad range of problems.

Dynamic Power Dissipation Control Method for Real-Time Processors Based on Hardware Multithreading

In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.

Local stability analysis of a low-dissipation cyclic refrigerator

We study the local stability near the maximum figure of merit for the low-dissipation cyclic refrigerator,where the irreversible dissipation occurs not only in the thermal contacts but also the adiabatic strokes.We find that the bounds of the coefficient of performance at a maximum figure of merit or maximum cooling rate in the presence of internal dissipation are identical to those in the corresponding absence of internal dissipation.Using two different scenarios,we prove the existence of a single stable steady state for the refrigerator,and clarify the role of internal dissipation on the stability of the thermodynamic steady state,showing that the speed of system evolution to the steady state decreases due to internal dissipation.

An extremely low power voltage reference with high PSRR for power-aware ASICs

An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio （PSRR） and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/℃ in a range from 25 to 100 ℃. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3,3 V, and PSRR is -49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm2. The circuit can be used as an elementary circuit block for power-aware ASICs.

A 3.125-Gb/s inductorless transimpedance amplifier for optical communication in 0.35μm CMOS

A 3.125-Gb/s transimpedance amplifier（TIA） for an optical communication system is realized in 0.35μm CMOS technology.The proposed TIA employs a regulated cascode configuration as the input stage, and adopts DC-cancellation techniques to stabilize the DC operating point.In addition,noise optimization is processed. The on-wafer measurement results show the transimpedance gain of 54.2 dBΩand -3 dB bandwidth of 2.31 GHz.The measured average input referred noise current spectral density is about 18.8 pA/（？）.The measured eye diagram is clear and symmetrical for 2.5-Gb/s and 3.125-Gb/s PRBS.Under a single 3.3-V supply voltage,the TIA consumes only 58.08 mW,including 20 mW from the output buffer.The whole die area is 465×435μm^2.