Design and Test of a CMOS Low Noise Amplifier in Bluetooth Transceiver

A RF low noise amplifier,integrated in a single bluetooth transceiver chip and fabricated in 0.35μm digital CMOS technology,is presented.Under the consideration of ESD protection and package,design methodology is discussed from the aspects of noise optimization,impedance match,and forward gain.At 2.05GHz,the measured S 11 is -6.4dB, S 21 is 11dB with 3dB-BW of 300MHz,and NF is about 5.3dB.It indicates that comprehensive consideration of parasitics,package model,and reasonable process is necessary for RF circuit design.

OPTIMIZATION DESIGN METHOD FOR INPUT IMPEDANCE MATCHING NETWORK OF LOW NOISE AMPLIFIER

According to the theories of optimal noise match and optimal power match, a method for calculating the optimal source impedance of low noise amplifier （LNA） is proposed based on the input reflection coefficient S11. Moreover.with the help of Smith chart, the calculation process is detailed, and the trade-off between the lowest noise figure and the maximum power gain is obtained during the design of LNA input impedance matching network. Based on the Chart 0. 35-μm CMOS process, a traditional cascode LNA circuit is designed and manufactured. Simulation and experimental results have a good agreement with the theoretical analysis, thus proving the correctness of theoretical analysis and the feasibility of the method.

Design of Low-Voltage Low Noise Amplifiers with High Linearity

A CMOS radio frequency low noise amplifier with high linearity and low operation voltage of less than 1.0V is presented.In this circuit,an auxiliary MOSFET in the triode region is used to boost the linearity.Simulation shows that this method can boost the input-referred 3rd-order intercept point with much less power dissipation than that of traditional power/linearity tradeoff solution which pays at least 1dB power for 1dB linearity improvement.It is also shown that the size of the common-gate PMOS transistor needs to be optimized to reduce its loaded input impedance so as not to degrade the linearity due to high voltage gain at its source terminal.The simulation is carried out with TSMC 0.18μm RF CMOS technology and SpectreRF.

CMOS Dual-Band Low Noise Amplifer

A CMOS dual-band low noise amplifer (LNA) design is presented.The purpose of th is work is intended to substitute only one LNA for two individual LNA's in dual -band transceivers for applications such as wireless local area network complying with both IEEE 802.11a and 802.11b/g.Dua l-band simultaneous input power and noise matching and load shaping are discuss ed.The chip is implemented in 0.25μm CMOS mixed and RF process.The measured pe rformance is summarized and discussed.

Low noise,continuous-wave single-frequency 1.5-μm laser generated by a singly resonant optical parametric oscillator

We report a low noise continuous-wave （CW） single-frequency 1.5-μm laser source obtained by a singly resonant optical parametric oscillator （SRO） based on periodically poled lithium niobate （PPLN）. The SRO was pumped by a CW single-frequency Nd：YVO4 laser at 1.06μm. The 1.02 W of CW single-frequency signal laser at 1.5 μm was obtained at pump power of 6 W. At the output power of around 0.75 W, the power stability was better than ±l.5% and no mode-hopping was observed in 30 min and frequency stability was better than 8.5 MHz in 1 min. The signal wavelength could be tuned from 1.57 to 1.59 μm by varying the PPLN temperature. The 1.5-μm laser exhibits low noise characteristics, the intensity noise of the laser reaches the shot noise limit （SNL） at an analysis frequency of 4 MHz and the phase noise is less than 1 dB above the SNL at analysis frequencies above 10 MHz.

Design and analysis on four stage SiGe HBT low noise amplifier

Focusing on the linearity shortcoming on a bipolar low noise amplifier(LNA),a new 6 ~14GHz four stage SiGe HBT LNA is proposed.This amplifier adopts a method of gain allocation on multiple stages to avoid the limitation on linearity especially with the addition of negative gain on the third stage.To realize gain flatness,extra zero is introduced to compensate the gain roll-off formed by pole,and local shunt-shunt negative feedback is used to widen the bandwidth as well as optimize circuit' s noise.Simulated results have shown that in 6 ~14GHz,this circuit achieves noise figure(NF) less than 3dB,gain of 17.8dB(+0.2dB),input and output reflection parameters of less than- 10 dB,and the K factor is above 1.15.

A 400 MHz Low Noise Amplifier at Cryogenic Temperature for Superconductor Filter System

A cryogenic low noise amplifier （LNA） using Agilent high electron mobility transistor （HEMT） for 380 MHzto 480 MHz is designed and fabricated, and the excellent cryogenic performance in superconducting receiver front-end for communication system is achieved. A special input impedance matching topology is implemented to provide low noise figure （NF） and good input matching in this cryogenic LNA design. The measurement results show that the NF is within 0.25 dB from the minimum NF of a single transistor, the power gain is above 20 dB, the flatness is within 1 dB, and the maximum input return loss is lower than -20 dB in bandwidth.

Analysis, Design and Implementation of SiGe Wideband Dual-Feedback Low Noise Amplifier

A wideband dual-feedback low noise amplifier （LNA） was analyzed, designed and implemented using SiGe heterojunction bipolar transistor （HBT） technology. The design analysis in terms of gain, input and output matching, noise and poles for the amplifier was presented in detail. The area of the complete chip die, including bonding pads and seal ring, was 655 μm × 495 μm. The on-wafer measurements on the fabricated wideband LNA sample demonstrated good performance： a small-signal power gain of 33 dB with 3-dB bandwidth at 3.3 GHz was achieved; the input and output return losses were better than - 10 dB from 100 MHz to 4 GHz and to 6 GHz, respectively; the noise figure was lower than 4.25 dB from 100 MHz to 6 GHz; with a 5 V supply, the values of OPtdB and OIP3 were 1.7 dBm and 11 dBm at 3-dB bandwidth, respectively.

New low noise interface circuit for detecting weak current of micro-sensors

A new low noise interface circuit for detecting weak current of micro-sensors is designed.By using the transimpedance amplifier to substitute the charge amplifier,the closed-loop circuit can avoid the phase error of the charge amplifier.Therefore,the phase compensation devices will be cancelled,because there is no phase transformation through the transimpedance amplifier.As well as,by using CCCII devices to implement the high value feedback resistor of the impedance amplifier,the noise of the I-V transformation devices is reduced,comparing with the passive resistor.The floating resistor is easy to be integrated into chips,making the integration of the interface circuit of the intelligent sensors increase.Through the simulation,the phase error of the charge amplifier is almost 9°at 2 kHz and it changes with the working frequency of the micro-sensors making the phase compensation not easy.The value of the floating resistor is 250 kΩ where the bias current is 50 μA.The noise of the active resistor is 0.037 fV2/Hz,comparing with the noise of the passive resistor,which is 4.14 fV2/Hz.

Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point （IPldn） of-11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.

Low Noise Readout Circuit for Biosensor SoC

Presented is a low noise interface circuit that is tuned to the needs of self-assembly monolayers biosensor SoC. The correlated double sampling(CDS) unit of the readout circuit can reduce 1/f noise, KTC noise and fixed noise of micro arrays effectively. The circuit is simulated in a 0.6 μm/level 7 standard CMOS process, and the simulated results show the output voltage has a good linearity with the transducing current of the micro arrays. This is a novel circuit including four amplifiers sharing a common half-circuit and the noise reducing CDS unit. It could be widely used for micro array biosensors.

A wideband CMOS variable gain low noise amplifier

In this paper, a novel structure of linear-in-dB gain control is introduced. Based on this structure, a wideband variable gain low noise amplifier （VGLNA） has been designed and implemented in 0.18μm RF CMOS technology. The measured resuhs show a good linear-in-dB gain control characteristic with 15 dB dynamic range. It can operate in the frequency range of MHz and consumes 30mW from 1.8V power supply. The minimum noise figure is 4.1 dB at the 48 - 860 maximum gain and the input P1dB is greater than - 16.5dBm.

Design of 5GHz low noise amplifier with HBM SiGe 0. 13μm BiCMOS process

A fully integrated low noise amplifier( LNA) for WLAN 802. 11 ac is presented in this article.A cascode topology combining BJT and MOS transistor is used for better performance. An inductive source degeneration is chosen to get 50 Ohm impedance matching at the input. The noise contribution of common gate transistor is analyzed for the first time. The designed LNA is verified with IBM silicon-germanium(SiGe ) 0. 13μm BiCMOS process. The measured results show that the designed LNA has the gain of 13 dB and NF of 2. 8 dB at the center frequency of 5. 5 GHz. The input reflection S11 and output reflection S22 are equal to-19 dB and-11 dB respectively. The P-1 dB and IIP3 are-8. 9 dBm and 6. 6 dBm for the linearity performance respectively. The power consumption is only 1. 3 mW under the 1. 2 V supply. LNA achieves high gain,low noise,and high linearity performance,allowing it to be used for the WLAN 802. 11 ac applications.

A compact and reconfigurable low noise amplifier employing combinational active inductors and composite resistors feedback techniques

A compact and reconfigurable low noise amplifier(LNA)is proposed by combining an input transistor,composite transistors with Darlington configuration as the amplification and output transistor,T-type structure composite resistors instead of a simplex structure resistor,a shunt inductor feedback realized by a tunable active inductor(AI),a shunt inductor peaking technique realized by another tunable AI.The division and collaboration among different resistances in the T-type structure composite resistor realize simultaneously input impedance matching,output impedance matching and good noise performance;the shunt feedback and peaking technique using two tunable AIs not only extend frequency bandwidth and improve gain flatness,but also make the gain and frequency band can be tuned simultaneously by the external bias of tunable AIs;the Darlington configuration of composite transistors provides high gain;furthermore,the adoption of the small size AIs instead of large size passive spiral inductor,and the use of composite resistors make the LNA have a small size.The LNA is fabricated and verified by GaAs/InGaP hetero-junction bipolar transistor(HBT)process.The results show that at the frequency of 7 GHz,the gain S_(21)is maximum and up to 19 dB;the S_(21)can be tuned from 17 dB to 19 dB by tuning external bias of tunable AIs,that is,the tunable amount of S_(21)is 2 dB,and similarly at 8 GHz;the tunable range of 3 dB bandwidth is 1 GHz.In addition,the gain S_(21)flatness is better than 0.4 dB under frequency from 3.1 GHz to 10.6 GHz;the size of the LNA only has 760μm×1260μm(including PADs).Therefore,the proposed strategies in the paper provide a new solution to the design of small size and reconfigurable ultra-wideband(UWB)LNA and can be used further to adjust the variations of gain and bandwidth of radio frequency integrated circuits(RFICs)due to package,parasitic and the variation of fabrication process and temperature.

Optimum Design for a Low Noise Amplifier in S-Band

An optimum design of a low noise amplifier （LNA） in S-band working at 2-4 GHz is described. Choosing FHC40LG high electronic mobility transistor （HEMT）, the noise figure of the designed amplifier simulated by Microwave Office is no more than 1.5 dB, meanwhile the gain is no less than 20 dB in the given bandwidth. The simulated results agree with the performance of the transistor itself well in consideration of its own minimum noise figure （0.3 dB） and associated gain （15.5 dB）. Simultaneously, the stability factor of the designed amplifier is no less than 1 in the given bandwidth.

Design and performance of a high-speed and low-noise preamplifier for SiPM

Considering the R&D for upgrading the K^(0)_(L) andμdetectors in the Belle II experiment using a scintillator and silicon pho-tomultiplier(SiPM),we designed a compact high-speed and low-noise preamplifier.The preamplifier demonstrated a good gain stability,bandwidth of 426 MHz,baseline noise level ofσ≈0.6 mV,dynamic range of up to170 mV of the input signal amplitude,good time resolution of 20 ps,and it can be comprehensively applied to SiPMs.Adopting pole-zero-cancelation in the preamplifier reduces both the rise and fall times of the SiPM signal,which can significantly improve the time resolution and reduce the pile-up when using a large SiPM or an array of SiPMs.Various combinations of the preamplifier and several types of SiPMs demonstrated time resolutions better than 50 ps for most cases;when the number of detected photons was larger than 60,a time resolution of approximately 25 ps was achieved.

Low-noise,low-power-consumption seafloor vector magnetometer

The seafloor vector magnetometer is an effective tool for marine geomagnetic surveys and seafloor magnetotelluric(MT)detection.However,the noise,power consumption,cost,and volume characteristics of existing seafloor vector magnetometers are insufficient for practical use.Therefore,a low-noise,low-power-consumption seafloor vector magnetometer that can be used for data acquisition of deep-ocean geomagnetic vector components is developed and presented.A seafloor vector magnetometer mainly consists of a fluxgate sensor,data acquisition module,acoustic release module,glass sphere,frame,burn-wire release,and anchor.A new low-noise data acquisition module and a fluxgate sensor greatly reduce power consumption.Furthermore,compact size is achieved by integrating an acoustic telemetry module and replacing the acoustic release with an external burn-wire release.The new design and magnetometer characteristics reduce the volume of the instrument and the cost of hardware considerably,thereby improving the integrity and deployment efficiency of the equipment.Theoretically,it can operate for 90 days underwater at a maximum depth of 6000 m.The seafloor vector magnetometer was tested in the South China Sea and the Philippine Sea and obtained high-quality geomagnetic data.The deep-water environment facilitates magnetic field data measurements,and the magnetometer has an approximate noise level of 10 pT/rt(Hz)@1 Hz,a peak-to-peak value error of 0.2 nT,and approximate power consumption of 200 mW.The fluxgate sensor can measure the magnetic field in the lower frequency band and realize geomagnetic field measurements over prolonged periods.

TRPV4-induced Neurofilament Injury Contributes to Memory Impairment after High Intensity and Low Frequency Noise Exposures

Objective Exposure to high intensity, low frequency noise(HI-LFN) causes vibroacoustic disease(VAD),with memory deficit as a primary non-auditory symptomatic effect of VAD. However, the underlying mechanism of the memory deficit is unknown. This study aimed to characterize potential mechanisms involving morphological changes of neurons and nerve fibers in the hippocampus, after exposure to HILFN.Methods Adult wild-type and transient receptor potential vanilloid subtype 4 knockout(TRPV4^(-/-)) mice were used for construction of the HI-LFN injury model. The new object recognition task and the Morris water maze test were used to measure the memory of these animals. Hemoxylin and eosin and immunofluorescence staining were used to examine morphological changes of the hippocampus after exposure to HI-LFN.Results The expression of TRPV4 was significantly upregulated in the hippocampus after HI-LFN exposure. Furthermore, memory deficits correlated with lower densities of neurons and neurofilamentpositive nerve fibers in the cornu ammonis 1(CA1) and dentate gyrus(DG) hippocampal areas in wildtype mice. However, TRPV4^(-/-)mice showed better performance in memory tests and more integrated neurofilament-positive nerve fibers in the CA1 and DG areas after HI-LFN exposure.Conclusion TRPV4 up-regulation induced neurofilament positive nerve fiber injury in the hippocampus,which was a possible mechanism for memory impairment and cognitive decline resulting from HI-LFN exposure. Together, these results identified a promising therapeutic target for treating cognitive dysfunction in VAD patients.

Low Noise Distributed Amplifiers Using a Novel Composite-Channel GaN HEMTs

Low noise distributed amplifiers （DAs） using the novel low noise composite-channel Al0.3 Ga0.7N/ml0.05 Ga0.95 N/ GaN HEMTs （CC-HEMTs） with 1μm-gate-length are designed and fabricated. Simulated and measured results of the DAs are characterized. The measured results show that the low noise DAs have input and output VSWR （voltage standing wave ratio） of less than 2.0,associated gain of more than 7.0dB and gain ripple of less than ldB in the frequency range from 2 to 10GHz. Noise figure of the DAs is less than 5dB in the frequency range from 2 to 6GHz,and less than 6.5dB in the frequency range from 2 to 10GHz. The measured results agree well with the simulated ones.

Implementation and noise optimization of a 433 MHz low power CMOS LNA

A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signal and RF （ radio frequency） CMOS process. The optimal noise performance of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA. The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB. The S21 is equal to 16 dB, S11 = -11 dB, S22 = -9 dB, and the inverse isolation is 35 dB. The measured input 1-dB compression point （PtdB） and input third-order intermodulation product （IIP3）are - 13 dBm and -3 dBm, respectively. The chip area is 0. 55 mm × 1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.