Design and Test of a CMOS Low Noise Amplifier in Bluetooth Transceiver

A RF low noise amplifier,integrated in a single bluetooth transceiver chip and fabricated in 0.35μm digital CMOS technology,is presented.Under the consideration of ESD protection and package,design methodology is discussed from the aspects of noise optimization,impedance match,and forward gain.At 2.05GHz,the measured S 11 is -6.4dB, S 21 is 11dB with 3dB-BW of 300MHz,and NF is about 5.3dB.It indicates that comprehensive consideration of parasitics,package model,and reasonable process is necessary for RF circuit design.

OPTIMIZATION DESIGN METHOD FOR INPUT IMPEDANCE MATCHING NETWORK OF LOW NOISE AMPLIFIER

According to the theories of optimal noise match and optimal power match, a method for calculating the optimal source impedance of low noise amplifier （LNA） is proposed based on the input reflection coefficient S11. Moreover.with the help of Smith chart, the calculation process is detailed, and the trade-off between the lowest noise figure and the maximum power gain is obtained during the design of LNA input impedance matching network. Based on the Chart 0. 35-μm CMOS process, a traditional cascode LNA circuit is designed and manufactured. Simulation and experimental results have a good agreement with the theoretical analysis, thus proving the correctness of theoretical analysis and the feasibility of the method.

Design of Low-Voltage Low Noise Amplifiers with High Linearity

A CMOS radio frequency low noise amplifier with high linearity and low operation voltage of less than 1.0V is presented.In this circuit,an auxiliary MOSFET in the triode region is used to boost the linearity.Simulation shows that this method can boost the input-referred 3rd-order intercept point with much less power dissipation than that of traditional power/linearity tradeoff solution which pays at least 1dB power for 1dB linearity improvement.It is also shown that the size of the common-gate PMOS transistor needs to be optimized to reduce its loaded input impedance so as not to degrade the linearity due to high voltage gain at its source terminal.The simulation is carried out with TSMC 0.18μm RF CMOS technology and SpectreRF.

Design and analysis on four stage SiGe HBT low noise amplifier

Focusing on the linearity shortcoming on a bipolar low noise amplifier(LNA),a new 6 ~14GHz four stage SiGe HBT LNA is proposed.This amplifier adopts a method of gain allocation on multiple stages to avoid the limitation on linearity especially with the addition of negative gain on the third stage.To realize gain flatness,extra zero is introduced to compensate the gain roll-off formed by pole,and local shunt-shunt negative feedback is used to widen the bandwidth as well as optimize circuit' s noise.Simulated results have shown that in 6 ~14GHz,this circuit achieves noise figure(NF) less than 3dB,gain of 17.8dB(+0.2dB),input and output reflection parameters of less than- 10 dB,and the K factor is above 1.15.

A 400 MHz Low Noise Amplifier at Cryogenic Temperature for Superconductor Filter System

A cryogenic low noise amplifier （LNA） using Agilent high electron mobility transistor （HEMT） for 380 MHzto 480 MHz is designed and fabricated, and the excellent cryogenic performance in superconducting receiver front-end for communication system is achieved. A special input impedance matching topology is implemented to provide low noise figure （NF） and good input matching in this cryogenic LNA design. The measurement results show that the NF is within 0.25 dB from the minimum NF of a single transistor, the power gain is above 20 dB, the flatness is within 1 dB, and the maximum input return loss is lower than -20 dB in bandwidth.

Analysis, Design and Implementation of SiGe Wideband Dual-Feedback Low Noise Amplifier

A wideband dual-feedback low noise amplifier （LNA） was analyzed, designed and implemented using SiGe heterojunction bipolar transistor （HBT） technology. The design analysis in terms of gain, input and output matching, noise and poles for the amplifier was presented in detail. The area of the complete chip die, including bonding pads and seal ring, was 655 μm × 495 μm. The on-wafer measurements on the fabricated wideband LNA sample demonstrated good performance： a small-signal power gain of 33 dB with 3-dB bandwidth at 3.3 GHz was achieved; the input and output return losses were better than - 10 dB from 100 MHz to 4 GHz and to 6 GHz, respectively; the noise figure was lower than 4.25 dB from 100 MHz to 6 GHz; with a 5 V supply, the values of OPtdB and OIP3 were 1.7 dBm and 11 dBm at 3-dB bandwidth, respectively.

Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point （IPldn） of-11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.

Design of 5GHz low noise amplifier with HBM SiGe 0. 13μm BiCMOS process

A fully integrated low noise amplifier( LNA) for WLAN 802. 11 ac is presented in this article.A cascode topology combining BJT and MOS transistor is used for better performance. An inductive source degeneration is chosen to get 50 Ohm impedance matching at the input. The noise contribution of common gate transistor is analyzed for the first time. The designed LNA is verified with IBM silicon-germanium(SiGe ) 0. 13μm BiCMOS process. The measured results show that the designed LNA has the gain of 13 dB and NF of 2. 8 dB at the center frequency of 5. 5 GHz. The input reflection S11 and output reflection S22 are equal to-19 dB and-11 dB respectively. The P-1 dB and IIP3 are-8. 9 dBm and 6. 6 dBm for the linearity performance respectively. The power consumption is only 1. 3 mW under the 1. 2 V supply. LNA achieves high gain,low noise,and high linearity performance,allowing it to be used for the WLAN 802. 11 ac applications.

A compact and reconfigurable low noise amplifier employing combinational active inductors and composite resistors feedback techniques

A compact and reconfigurable low noise amplifier(LNA)is proposed by combining an input transistor,composite transistors with Darlington configuration as the amplification and output transistor,T-type structure composite resistors instead of a simplex structure resistor,a shunt inductor feedback realized by a tunable active inductor(AI),a shunt inductor peaking technique realized by another tunable AI.The division and collaboration among different resistances in the T-type structure composite resistor realize simultaneously input impedance matching,output impedance matching and good noise performance;the shunt feedback and peaking technique using two tunable AIs not only extend frequency bandwidth and improve gain flatness,but also make the gain and frequency band can be tuned simultaneously by the external bias of tunable AIs;the Darlington configuration of composite transistors provides high gain;furthermore,the adoption of the small size AIs instead of large size passive spiral inductor,and the use of composite resistors make the LNA have a small size.The LNA is fabricated and verified by GaAs/InGaP hetero-junction bipolar transistor(HBT)process.The results show that at the frequency of 7 GHz,the gain S_(21)is maximum and up to 19 dB;the S_(21)can be tuned from 17 dB to 19 dB by tuning external bias of tunable AIs,that is,the tunable amount of S_(21)is 2 dB,and similarly at 8 GHz;the tunable range of 3 dB bandwidth is 1 GHz.In addition,the gain S_(21)flatness is better than 0.4 dB under frequency from 3.1 GHz to 10.6 GHz;the size of the LNA only has 760μm×1260μm(including PADs).Therefore,the proposed strategies in the paper provide a new solution to the design of small size and reconfigurable ultra-wideband(UWB)LNA and can be used further to adjust the variations of gain and bandwidth of radio frequency integrated circuits(RFICs)due to package,parasitic and the variation of fabrication process and temperature.

A wideband CMOS variable gain low noise amplifier

In this paper, a novel structure of linear-in-dB gain control is introduced. Based on this structure, a wideband variable gain low noise amplifier （VGLNA） has been designed and implemented in 0.18μm RF CMOS technology. The measured resuhs show a good linear-in-dB gain control characteristic with 15 dB dynamic range. It can operate in the frequency range of MHz and consumes 30mW from 1.8V power supply. The minimum noise figure is 4.1 dB at the 48 - 860 maximum gain and the input P1dB is greater than - 16.5dBm.

Optimum Design for a Low Noise Amplifier in S-Band

An optimum design of a low noise amplifier （LNA） in S-band working at 2-4 GHz is described. Choosing FHC40LG high electronic mobility transistor （HEMT）, the noise figure of the designed amplifier simulated by Microwave Office is no more than 1.5 dB, meanwhile the gain is no less than 20 dB in the given bandwidth. The simulated results agree with the performance of the transistor itself well in consideration of its own minimum noise figure （0.3 dB） and associated gain （15.5 dB）. Simultaneously, the stability factor of the designed amplifier is no less than 1 in the given bandwidth.

A full W-band low noise amplifier module for millimeter-wave applications

A full W-band low noise amplifier （LNA） module is designed and fabricated. A broadband transition is introduced in this module. The proposed transition is designed, optimized based on the results from numerical simulations. The results show that 1 dB bandwidth of the transition ranges from 61 to 117 GHz. For the purpose of verification, two transitions in back-to-back connection are measured. The results show that transmission loss is only about 0.9-1.7 dB. This transition is used to interface integrated circuits to waveguide components. The characteristic of the LNA module is measured after assembly. It exhibits a broad bandwidth of 75 to 110 GHz, and has a small signal gain above 21 dB. The noise figure is lower than 5.2 dB throughout the entire W-band （below 3 dB from 89 to 95 GHz） at room temperature. The proposed LNA module exhibits potential for millimeter wave applications due to its high small signal gain, low noise, and low DC power consumption.

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier（LNA）,designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure（NF） of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point（IIP3） is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.

Design of low power common-gate low noise amplifier for 2.4 GHz wireless sensor network applications

This paper presents a differential low power low noise amplifier designed for the wireless sensor network （WSN） in a TSMC 0.18μm RF CMOS process.A two-stage cross-coupling cascaded common-gate（CG） topology has been designed as the amplifier.The first stage is a capacitive cross-coupling topology.It can reduce the power and noise simultaneously.The second stage is a positive feedback cross-coupling topology,used to set up a negative resistance to enhance the equivalent Q factor of the inductor at the load to improve the gain of the LNA.A differential inductor has been designed as the load to achieve reasonable gain.This inductor has been simulated by the means of momentum electromagnetic simulation in ADS.A ＂double-π＂ circuit model has been built as the inductor model by iteration in ADS.The inductor has been fabricated separately to verify the model. The LNA has been fabricated and measured.The LNA works well centered at 2.44 GHz.The measured gain S_（21） is variable with high gain at 16.8 dB and low gain at 1 dB.The NF（noise figure） at high gain mode is 3.6 dB,the input referenced 1 dB compression point（IP1dB） is about -8 dBm and the IIP3 is 2 dBm at low gain mode.The LNA consumes about 1.2 mA current from 1.8 V power supply.

A 0.18μm CMOS dual-band low power low noise amplifier for a global navigation satellite system

This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed. The relevant parameter analysis and the details of circuit design are presented. The test chip was implemented in a TSMC 0.18 μm 1P4M RF CMOS process. The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz. The measured noise figure is around 1.5-1.7 dB on both bands. The LNA consumes less than 4.3 mA of current from a 1.8 V power supply. The measurement results show consistency with the design. And the LNA can fully satisfy the demands of the GNSS receiver.

A 2.4-GHz low power dual gain low noise amplifier for ZigBee

This paper presents a fully differential dual gain low noise amplifier（DGLNA） for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analyzed.Circuit design details within the guidelines of the analysis are presented.The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process.The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss.In high gain mode, the measured noise figure（NF） is 2.3-3 dB in the whole 2.45-GHz ISM band.The measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, respectively.The DGLNA consumes 2 mA of current from a 1.8 V power supply.

Design of a 0.5 V CMOS cascode low noise amplifier for multi-gigahertz applications

This paper presents the design of 0.5 V multi-gigahertz cascode CMOS LNA for low power wireless communication. By splitting the direct current through conventional cascode topology, the constraint of stacking- MOS structure for supply voltage has been removed and based on forward-body-bias technology, the circuit can operate at 0.5 V supply voltage. Design details and RF characteristics have been investigated in this paper. To verify the investigation, a 0.5 V 5.4 GHz LNA has been fabricated through 0.18 μm CMOS technology and measured. Measured results show that it obtains 9.1 dB gain, 3 dB NF with 0.5 V voltage and 2.5 mW power dissipation. The measured IIP3 is -3.5 dBm. Compared with previously published cascode LNA, it achieves the lowest supply voltage and lowest power dissipation with competitive RF performances.

Implementation and noise optimization of a 433 MHz low power CMOS LNA

A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signal and RF （ radio frequency） CMOS process. The optimal noise performance of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA. The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB. The S21 is equal to 16 dB, S11 = -11 dB, S22 = -9 dB, and the inverse isolation is 35 dB. The measured input 1-dB compression point （PtdB） and input third-order intermodulation product （IIP3）are - 13 dBm and -3 dBm, respectively. The chip area is 0. 55 mm × 1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.

A Super-Low-Noise,High-Gain MMIC LNA

A two-stage monolithic low noise amplifier is developed for satellite communication applications,using a 0.5μm enhancement PHEMT technology. The on-chip matched amplifier employs lumped elements to reduce the circuit size, and shows a 5012 noise figure less than 0.9dB, gain greater than 26dB, and return loss less than - 10dB in the S-C band range of 3.5 to 4. 3GHz. The noise figure obtained here is the best result ever reported to date of an MMIC LNA with a gain of more than 20dB for the S-C band frequency range. It is attributed to the low noise performance of the enhancement PHEMT transistor and minimized parasitic resistance of the input match network by a common series source inductor and a unique divided resistance at the drain.

CMOS Dual-Band Low Noise Amplifer

A CMOS dual-band low noise amplifer (LNA) design is presented.The purpose of th is work is intended to substitute only one LNA for two individual LNA's in dual -band transceivers for applications such as wireless local area network complying with both IEEE 802.11a and 802.11b/g.Dua l-band simultaneous input power and noise matching and load shaping are discuss ed.The chip is implemented in 0.25μm CMOS mixed and RF process.The measured pe rformance is summarized and discussed.