Low-Power Design of Ethernet Data Transmission

For the reliability and power consumption issues of Ethernet data transmission based on the field programmable gate array （FPGA）, a low-power consumption design method is proposed, which is suitable for FPGA implementation. To reduce the dynamic power consumption of integrated circuit （IC） design, the proposed method adopts the dynamic control of the clock frequency. For most of the time, when the port is in the idle state or lower-rate state, users can reduce or even turn off the reading clock frequency and reduce the clock flip frequency in order to reduce the dynamic power consumption. When the receiving rate is high, the reading clock frequency will be improved timely to ensure that no data will lost. Simulated and verified by Modelsim, the proposed method can dynamically control the clock frequency, including the dynamic switching of high-speed and low-speed clock flip rates, or stop of the clock flip.

Design of Low-Power Data Logger of Deep Sea for Long-Term Field Observation

This paper describes the implementation of a data logger for the real-time in-situ monitoring of hydrothermal systems. A compact mechanical structure ensures the security and reliability of data logger when used under deep sea. The data logger is a battery powered instrument, which can connect chemical sensors （pH electrode, H2S electrode, H2 electrode） and temperature sensors. In order to achieve major energy savings, dynamic power management is implemented in hardware design and software design. The working current of the data logger in idle mode and active mode is 15 μA and 1.44 mA respectively, which greatly extends the working time of battery. The data logger has been successftdly tested in the first Sino-American Cooperative Deep Submergence Project from August 13 to September 3, 2005.

On-Chip Micro Temperature Controllers Based on Freestanding Thermoelectric Nano Films for Low-Power Electronics

Multidimensional integration and multifunctional com-ponent assembly have been greatly explored in recent years to extend Moore’s Law of modern microelectronics.However,this inevitably exac-erbates the inhomogeneity of temperature distribution in microsystems,making precise temperature control for electronic components extremely challenging.Herein,we report an on-chip micro temperature controller including a pair of thermoelectric legs with a total area of 50×50μm^(2),which are fabricated from dense and flat freestanding Bi2Te3-based ther-moelectric nano films deposited on a newly developed nano graphene oxide membrane substrate.Its tunable equivalent thermal resistance is controlled by electrical currents to achieve energy-efficient temperature control for low-power electronics.A large cooling temperature difference of 44.5 K at 380 K is achieved with a power consumption of only 445μW,resulting in an ultrahigh temperature control capability over 100 K mW^(-1).Moreover,an ultra-fast cooling rate exceeding 2000 K s^(-1) and excellent reliability of up to 1 million cycles are observed.Our proposed on-chip temperature controller is expected to enable further miniaturization and multifunctional integration on a single chip for microelectronics.

Low-power system model for quantum entangled photon-pair source

The quantum entangled photon-pair source,as an essential component of optical quantum systems,holds great potential for applications such as quantum teleportation,quan-tum computing,and quantum imaging.The current workhorse technique for preparing photon pairs involves performing spon-taneous parametric down conversion(SPDC)in bulk nonlinear crystals.However,the current power consumption and cost of preparing entangled photon-pair sources are relatively high,pos-ing challenges to their integration and scalability.In this paper,we propose a low-power system model for the quantum entan-gled photon-pair source based on SPDC theory and phase matching technology.This model allows us to analyze the per-formance of each module and the influence of component cha-racteristics on the overall system.In our experimental setup,we utilize a 5 mW laser diode and a typical type-II barium metabo-rate(BBO)crystal to prepare an entangled photon-pair source.The experimental results are in excellent agreement with the model,indicating a significant step towards achieving the goal of low-power and low-cost entangled photon-pair sources.This achievement not only contributes to the practical application of quantum entanglement lighting,but also paves the way for the widespread adoption of optical quantum systems in the future.

New design solutions for low-power energy production in water pipe systems

This study is the result of ongoing research for a European Union 7th Framework Program Project regarding energy converters for very low heads, and aims to analyze optimization of new cost-effective hydraulic turbine designs for possible implementation in water supply systems （WSSs） or in other pressurized water pipe infrastructures, such as irrigation, wastewater, or drainage systems. A new methodology is presented based on a theoretical, technical and economic analysis. Viability studies focused on small power values for different pipe systems were investigated. Detailed analyses of alternative typical volumetric energy converters were conducted on the basis of mathematical and physical fundamentals as well as computational fluid dynamics （CFD） associated with the interaction between the flow conditions and the system operation. Important constraints （e.g., size, stability, efficiency, and continuous steady flow conditions） can be identified and a search for alternative rotary yolumetric converters is being conducted. As promising cost-effective solutions for the coming years, adapted rotor-dynamic turbomachines and non-conventional axial propeller devices were analyzed based on the basic principles of pumps operating as turbines, as well as through an extensive comparison between simulations and experimental tests.

Low-power emerging memristive designs towards secure hardware systems for applications in internet of things

Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and inmemory computing(IMC),but there is a rising interest in using memristive technologies for security applications in the era of internet of things(IoT).In this review article,for achieving secure hardware systems in IoT,lowpower design techniques based on emerging memristive technology for hardware security primitives/systems are presented.By reviewing the state-of-the-art in three highlighted memristive application areas,i.e.memristive non-volatile memory,memristive reconfigurable logic computing and memristive artificial intelligent computing,their application-level impacts on the novel implementations of secret key generation,crypto functions and machine learning attacks are explored,respectively.For the low-power security applications in IoT,it is essential to understand how to best realize cryptographic circuitry using memristive circuitries,and to assess the implications of memristive crypto implementations on security and to develop novel computing paradigms that will enhance their security.This review article aims to help researchers to explore security solutions,to analyze new possible threats and to develop corresponding protections for the secure hardware systems based on low-cost memristive circuit designs.

Ethernet Controller SoC Design and Its Low-Power DFT Considerations

In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）, media access control （MAC） circuit and embedded memories such as static random access memory （SRAM）, read only memory （ROM） and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test （BIST）. By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology, the die area is 4.8×4.6 mm^2. Test results show that the maximum throughput of Ethemet packets may reach 7Mb·s^1.

Novel Design of Low-power Multiplex Differential Voltage Comparators

A novel design of multiplex differential voltage comparators(MDVC) is presented for reducing current and power dissipation. According to the special properties of relational operation and logical operation, parts of the comparators are redundant in some instances, and thus can be turned off. By selecting and switching the current routes, several effective differential pairs are biased by a single tail current stage-by-stage and the redundant comparators are turned off by cutting their tail currents. As a result, the quiescent current and power consumption are greatly decreased. The switching of current is achieved by the input differential pair transistors themselves and hence no extra switches are required. When a MDVC is used in a flash analog-to-digital converter(ADC), its current dissipation is much lower than that of the conventional comparators. This architecture can also be used in window-comparators, maximum or minimum comparators, and comparators for logical operations. The power dissipation in all these cases could be reduced significantly.

Design of low-offset low-power CMOS amplifier for biosensor application

A compacted and low-offset low-power CMOS am- plifier for biosensor application is presented in this paper. It includes a low offset Op-Amp and a high precision current reference. With a novel continuous-time DC offset rejection scheme, the IC achieves lower offset voltage and lower power consumption compared to previous designs. This configuration rejects large DC offset and drift that exist at the skin-electrode interface without the need of external components. The proposed amplifier has been implemented in SMIC 0.18-μm 1P6M CMOS technol-ogy, with an active silicon area of 100 μm by 120 μm. The back-annotated simulation results demonstrated the circuit features the systematic offset voltage less than 80 μV, the offset drift about 0.27 μV/℃ for temperature ranging from –30℃ to 100℃ and the total power dissipation consumed as low as 37.8 μW from a 1.8 V single supply. It dedicated to monitor low amplitude biomedical signals recording.

Design of a Low-Power CMOS LVDS I/O Interface Circuit

The paper presents the design and implementation of LVDS （low-voltage differential signaling） receiver circuit, fully compatible with LVDS standard. The proposed circuit is composed of the telescopic amplifier and the comparator with internal hysteresis. The receiver supports 3.5 Gbps data rate with 7.4 mA current at 1.8 V supply according to post-layout circuit simulations. The circuit has the power consumption of 13.1 MW. Comparing with the conventional circuit, the circuit is achieved to reduce the power consumption by 19.1% and the data rate by 14.3 %. The validity and effectiveness of the proposed circuit are verified through the circuit simulation with Samsung 0.18 μm CMOS （complementary metal-oxide-semiconductor） standard technology under the 1.8 V supply voltage.

Low-Power Digital Circuit Design with Triple-Threshold Voltage

Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

A Low-Power-Consumption 9bit 10MS/s Pipeline ADC for CMOS Image Sensors

A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure, and biasing all the cells with the same voltage bias source, which requires careful layout design and large capacitors. In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range. The ADC was implemented in a 0.18μm 4M-1 P CMOS process,and the experimental results indicate that it consumes only 7mW, which is much less than general pipeline ADCs. The ADC was used in a 300000 pixels CMOS image sensor.

水田动力底盘逆向建模与质心验证——基于Geomagic Design X

针对目前农业机械仿真和优化模型精度不高的问题,提出了一种构建精确模型的逆向建模方法。应用光学扫描仪采集点云数据,基于Geomagic Design X处理点云数据并重构零部件模型,在SolidWorks中完成水田动力底盘的装配。以VP6D-CQ型水田动力底盘为例,将测得的实际质心位置与所建的模型质心位置进行比较,并对提出的逆向建模方法进行了试验验证以及误差分析。结果表明:总质量、x坐标、y坐标、z坐标的误差值分别为4.55%、3.62%、2.23%、4.81%,误差值均在5%内。此方法可构建准确的三维模型,为后续仿真优化数据精确性奠定了基础,与传统的研发相比较,可缩短农业机械研发周期、降低设计成本。

A kind of low-power 10 Gbit/s CMOS 1∶4 demultiplexer

A 10 Gbit/s 1：4 demultiplexer（DEMUX） fabricated in 0. 18 μm CMOS （complementary metal-oxidesemiconductor transistor） technology for optical-fiber-link is presented. The system is constructed in tree-type structure and it includes a high-speed 1 ： 2 DEMUX, two low-speed 1 ： 2 DEMUXs, a divider, and input and output buffers for data and dock. To improve the circuit performance and reduce the power consumption, a latch structure with a common-gate topology and a single clock phase is employed in the high-speed 1 ： 2 DEMUX and the 5 GHz 1 ： 2 on-chip frequency divider, while dynamic CMOS logic is adopted in the low-speed l ： 2 DEMUXs. Measured results at 10 Gbit/s by 23^31 -1 pseudo random bit sequences （PRBS） via on-wafer testing indicate that it can work well with a power dissipation of less than 100 mW at 1.8 V supply voltage. The die area of the DEMUX is 0. 65 mm × 0. 75 mm.

App Designer辅助教学方法探索与实践——以软件无线电课程为例

软件无线电作为通信学科的必修课程,具有承上启下的重要作用。因课程原理抽象、理论公式复杂,学员在学习过程存在理解掌握难、实践应用难等问题。通过对当前软件无线电教学过程中存在的不足与困难进行分析,提出利用MATLAB App Designer辅助课程教学,从教学准备、课堂互动、自主实验、反馈提升四个方面开展课程教学改革。实践表明,该方法对于提升学员的工程思维、系统思维具有显著效果,同时可以增强学员理论联系实际的能力。

Low-power laser irradiation promotes the proliferation and osteogenic differentiation of human periodontal ligament cells via cyclic adenosine monophosphate

Retaining or improving periodontal ligament （PDL） function is crucial for restoring periodontal defects. The aim of this study was to evaluate the physiological effects of low-power laser irradiation （LPLI） on the proliferation and osteogenic differentiation of human PDL （hPDL） cells. Cultured hPDL cel Is were irradiated （660 nm） daily with doses of O, 1, 2 or 4 J .cm-2. Cell proliferation was evaluated by the 3-[4,5-dimethylthiazol-2-yl]-2,5-diphenyltetrazolium bromide （MTT） assay, and the effect of LPLI on osteogenic differentiation was assessed by Alizarin Red S staining and alkaline phosphatase （ALP） activity. Additionally, osteogenic marker gene expression was confirmed by real-time reverse transcription-polymerase chain reaction （RT-PCR）. Our data showed that LPLI at a dose of 2 J.cm-2 significantly promoted hPDL cell proliferation at days 3 and 5. In addition, LPLI at energy doses of 2 and 4 J.cm-2 showed potential osteogenic capacity, as it stimulated ALP activity, calcium deposition, and osteogenic gene expression. We also showed that cyclic adenosine monophosphate （cAMP） is a critical regulator of the LPLI-mediated effects on hPDL cells. This study shows that LPLI can promote the proliferation and osteogenic differentiation of hPDL cells. These results suggest the potential use of LPLI in clinical applications for periodontal tissue regeneration.

Modelling Study to Compare the Flow and Heat Transfer Characteristics of Low-Power Hydrogen,Nitrogen and Argon Arc-Heated Thrusters

A modelling study is performed to compare the plasma flow and heat transfer characteristics of low-power arc-heated thrusters （arcjets） for three different propellants： hydrogen, nitrogen and argon. The all-speed SIMPLE algorithm is employed to solve the governing equations, which take into account the effects of compressibility, Lorentz force and Joule heating, as well as the temperature- and pressure-dependence of the gas properties. The temperature, velocity and Mach number distributions calculated within the thruster nozzle obtained with different propellant gases are compared for the same thruster structure, dimensions, inlet-gas stagnant pressure and arc currents. The temperature distributions in the solid region of the anode-nozzle wall are also given. It is found that the flow and energy conversion processes in the thruster nozzle show many similar features for all three propellants. For example, the propellant is heated mainly in the near-cathode and constrictor region, with the highest plasma temperature appearing near the cathode tip; the flow transition from the subsonic to supersonic regime occurs within the constrictor region; the highest axial velocity appears inside the nozzle; and most of the input propellant flows towards the thruster exit through the cooler gas region near the anode-nozzle wall. However, since the properties of hydrogen, nitrogen and argon, especially their molecular weights, specific enthMpies and thermal conductivities, are different, there are appreciable differences in arcjet performance. For example, compared to the other two propellants, the hydrogen arcjet thruster shows a higher plasma temperature in the arc region, and higher axial velocity but lower temperature at the thruster exit. Correspondingly, the hydrogen arcjet thruster has the highest specific impulse and arc voltage for the same inlet stagnant pressure and arc current. The predictions of the modelling are compared favourably with available experimental results.

EXPERIMENTAL STUDY ON MACRO AND MICRO-STRUCTURE OF METALLIC PARTS BUILT BY LOW-POWER LASER CLADDING

A low-power CO_2 laser is used to deposit Fe powder and mixture of Fe andcarbon powder on substrates respectively, and the macro and micro-structure of the formed samplesare investigated. It is demonstrated that most grains of these samples are equi-axed. This isderived from the high nucleation velocity in the shallow melt pool besides rapid solidification ofthe liquid-state alloy or metal. Bainitic structure, combination of pearlite and ferrite structureand ferrite structure are seen respectively in the samples involving various amounts of carbon owingto no martensitic transformation in these small samples.

Transplantation of low-power laser-irradiated olfactory ensheathing cells to promote repair of spinal cord injury in rats

BACKGROUND： Previous studies have demonstrated that low-power laser （LPL） irradiation can promote the regeneration of peripheral nerves and central nerves, as well as influence cellular proliferation. Therefore, it is thought to be a potential treatment for spinal cord injury. OBJECTIVE： Utilizing histological observations and behavioral evaluations, the aim of this study was to investigate the influence of transplanted olfactory ensheathing cells （OECs）, irradiated by LPL, on functional repair of rats following transversal spinal cord injury. DESIGN, TIME AND SETTING： A randomized, controlled, animal experiment was performed at the animal experimental center in the First Affiliated Hospital of Xinjiang Medical University between January 2007 and February 2008. MATERIALS： A total of 52 Sprague Dawley rats were included in this experiment. Twelve rats were used to harvest OECs, some of which were irradiated by LPL on days 3, 5, and 7 in culture. The remaining 40 rats were used to establish T12 complete spinal cord transection injury. DMEM/F12 medium was purchased from Sigma, USA, Fluorogold was provided by Chemicon, USA, and the LY/JG650-D500-16 low-power laser was produced by Xi＇an Lingyue Electromechanical Science And Technology Co., Ltd., China. METHODS： The successful rat models were randomly divided into three groups： OEC transplantation, LPL-irradiated OEC transplantation, and control. These animals were microinjected with OEC suspension, LPL-irradiated OEC suspension, and DMEM/F12 medium （10μL） respectively 4 weeks after spinal cord was completely transected at the T12 level. MAIN OUTCOME MEASURES： Spinal cord injury was observed using hematoxylin-eosin staining Expression of nerve growth factor receptor p75 and glial fibrillary acidic protein were determined using immunohistochemical staining. Regeneration of spinal nerve fibers in rats was assayed by Fluorogold retrograde labeling method. Basso, Beattie and Bresnahan （BBB） scores were used to evaluate motor functions of rat lower limbs. RESULTS： Structural disturbances were observed following spinal cord injury in each group, and a large amount of scar tissue covered the broken ends, accompanied by porosis and inflammatory cell infiltration. Following OEC transplantation, the distal end connected to the proximal end. nerve growth factor receptor p75 and glial fibrillary acidic protein immunohistochemistry revealed positive OECs in the cephalad and caudal area of rats that received LPL-irradiated OEC transplantation. In the OECs group, only glial fibrillary acidic protein staining was observed. No staining was found in the control group. Neural fibers labeled with Fluorogold extended across the lesion area and into the cephalad and caudal area in the OECs and LPL-irradiated OECs groups, but were not present in the control group. BBB scores revealed statistically significant differences among the three groups （P 〈 0.05）： OECs irradiated by LPL group 〉 OECs group 〉 control group. CONCLUSION： Transplantation of OECs and LPL-irradiated OECs promoted functional repair in the injured spinal cord of rats, although LPL-irradiated OECs resulted in greater beneficial effects.

A low-power high-throughput link splitting router for NoCs

In this paper, we propose a technique for lowering the latency of the communication in a NoC （network on chip）. The technique, which can support two qualities of service （QoS）, i.e., the guaranteed throughput （GT） and best effort （BE）, is based on splitting a wider link into narrower links to increase throughput and decrease latency in the NoC. In addition, to ease the synchronization and reduce the crosstalk, we use the l-of-4 encoding for the smaller buses. The use of the encoding in the proposed NoC architecture considerably lowers the latency for both BE and GT packets. In addition, the bandwidth is increased while the power consumption of the links is reduced.