rMVP: A Memory-efficient, Visualization-enhanced, and Parallel-accelerated Tool for Genome-wide Association Study

Along with the develoipment of high-throughput sequencing technologies,both sample size and SNP number are increasing rapidly in genome-wide association studies(GWAS),and the associated computation is more challenging than ever.Here,we present a memory-efficient,visualization-enhanced,and parallel-accelerated R package called“r MVP”to address the need for improved GWAS computation.r MVP can 1)effectively process large GWAS data,2)rapidly evaluate population structure,3)efficiently estimate variance components by Efficient Mixed-Model Association e Xpedited(EMMAX),Factored Spectrally Transformed Linear Mixed Models(Fa ST-LMM),and Haseman-Elston(HE)regression algorithms,4)implement parallel-accelerated association tests of markers using general linear model(GLM),mixed linear model(MLM),and fixed and random model circulating probability unification(Farm CPU)methods,5)compute fast with a globally efficient design in the GWAS processes,and 6)generate various visualizations of GWASrelated information.Accelerated by block matrix multiplication strategy and multiple threads,the association test methods embedded in r MVP are significantly faster than PLINK,GEMMA,and Farm CPU_pkg.r MVP is freely available at https://github.com/xiaolei-lab/r MVP.

A Memory Efficient Belief Propagation Decoder for Polar Codes

Polar codes have become increasingly popular recently because of their capacity achieving property.In this paper,a memory efficient stage-combined belief propagation(BP) decoder design for polar codes is presented.Firstly,we briefly reviewed the conventional BP decoding algorithm.Then a stage-combined BP decoding algorithm which combines two adjacent stages into one stage and the corresponding belief message updating rules are introduced.Based on this stage-combined decoding algorithm,a memory-efficient polar BP decoder is designed.The demonstrated decoder design achieves 50%memory and decoding latency reduction in the cost of some combinational logic complexity overhead.The proposed decoder is synthesized under TSMC 45 nm Low Power CMOS technology.It achieves 0.96 Gb/s throughput with 14.2mm^2 area when code length N=2^(16)which reduces 51.5%decoder area compared with the conventional decoder design.