Interfacial and electrical properties of HfAIO/GaSb metal-oxide-semiconductor capacitors with sulfur passivation

Interfacial and electrical properties of HfAlO/GaSb metal-oxide-semiconductor capacitors(MOSCAPs) with sulfur passivation were investigated and the chemical mechanisms of the sulfur passivation process were carefully studied. It was shown that the sulfur passivation treatment could reduce the interface trap density Ditof the HfAlO/GaSb interface by 35% and reduce the equivalent oxide thickness(EOT) from 8 nm to 4 nm. The improved properties are due to the removal of the native oxide layer, as was proven by x-ray photoelectron spectroscopy measurements and high-resolution cross-sectional transmission electron microscopy(HRXTEM) results. It was also found that GaSb-based MOSCAPs with HfAlO gate dielectrics have interfacial properties superior to those using HfO2 or Al2O3 dielectric layers.

Mobility enhancement of strained GaSb p-channel metal-oxide-semiconductor field-effect transistors with biaxial compressive strain

Various biaxial compressive strained GaSb p-channel metal-oxide-semiconductor field-effect transistors （MOSFETs） are experimentally and theoretically investigated, The biaxial compressive strained GaSb MOSFETs show a high peak mobility of 638 cm2/V.s, which is 3.86 times of the extracted mobility of the fabricated GaSb MOSFETs without strain. Meanwhile, first principles calculations show that the hole effective mass of GaSb depends on the biaxial compressive strain. The biaxiai compressive strain brings a remarkable enhancement of the hole mobility caused by a significant reduction in the hole effective mass due to the modulation of the valence bands.

Hot-Carrier Effects on Total Dose Irradiated 65 nm n-Type Metal-Oxide-Semiconductor Field-Effect Transistors

The influence of total dose irradiation on hot-carrier reliability of 65 nm n-type metal-oxide-semiconductor field- effect transistors （nMOSFETs） is investigated. Experimental results show that hot-carrier degradations on ir- radiated narrow channel nMOSFETs are greater than those without irradiation. The reason is attributed to radiation-induced charge trapping in shallow trench isolation （STI）. The electric field in the pinch-off region of the nMOSFET is enhanced by radiation-induced charge trapping in STI, resulting in a more severe hot-carrier effect.

Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

In this paper, TiN/A1Ox gated A1GaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors （MOS- HFETs） were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 ℃ with the contact resistance approximately 1.6 Ω.mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/A1Ox gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AIGaN/GaN MOS-HFETs.

Positive Bias Temperature Instability and Hot Carrier Injection of Back Gate Ultra-thin-body In0.53Ga0.47As-on-Insulator n-Channel Metal-Oxide-Semiconductor Field-Effect Transistor

Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors （nMOSFETs） are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability （PBTI） and hot carrier injection （HCI） characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.

X-ray detection based on complementary metal-oxide-semiconductor sensors

Complementary metal-oxide-semiconductor(CMOS) sensors can convert X-rays into detectable signals; therefore, they are powerful tools in X-ray detection applications. Herein, we explore the physics behind X-ray detection performed using CMOS sensors. X-ray measurements were obtained using a simulated positioner based on a CMOS sensor, while the X-ray energy was modified by changing the voltage, current, and radiation time. A monitoring control unit collected video data of the detected X-rays. The video images were framed and filtered to detect the effective pixel points(radiation spots).The histograms of the images prove there is a linear relationship between the pixel points and X-ray energy. The relationships between the image pixel points, voltage, and current were quantified, and the resultant correlations were observed to obey some physical laws.

Capacitance characteristics of metal-oxide-semiconductor capacitors with a single layer of embedded nickel nanoparticles for the application of nonvolatile memory

This paper reports that metal-oxide-semiconductor （MOS） capacitors with a single layer of Ni nanopartictes were successfully fabricated by using electron-beam evaporation and rapid thermal annealing for application to nonvolatile memory. Experimental scanning electron microscopy images showed that Ni nanoparticles of about 5 nm in diameter were clearly embedded in the SiO2 layer on p-type Si （100）. Capacitance-voltage measurements of the MOS capacitor show large flat-band voltage shifts of 1.8 V, which indicate the presence of charge storage in the nickel nanoparticles. In addition, the charge-retention characteristics of MOS capacitors with Ni nanoparticles were investigated by using capacitance-time measurements. The results showed that there was a decay of the capacitance embedded with Ni nanoparticles for an electron charge after 104 s. But only a slight decay of the capacitance originating from hole charging was observed. The present results indicate that this technique is promising for the efficient formation or insertion of metal nanoparticles inside MOS structures.

Influences of fringing capacitance on threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor

Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor（MOSFET） are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.

GaSb p-channel metal-oxide-semiconductor field-effect transistor and its temperature dependent characteristics

GaSb p-channel metal-oxide-semiconductor field-effect transistors （MOSFETs） with an atomic layer deposited Al2O3 gate dielectric and a self-aligned Si-implanted source/drain are experimentally demonstrated. Temperature dependent electrical characteristics are investigated. Different electrical behaviors are observed in two temperature regions, and the un- derlying mechanisms are discussed. It is found that the reverse-bias pn junction leakage of the drain/substrate is the main component of the off-state drain leakage current, which is generation-current dominated in the low temperature regions and is diffusion-current dominated in the high temperature regions. Methods to further reduce the off-state drain leakage current are given.

The study on mechanism and model of negative bias temperature instability degradation in P-channel metal-oxide-semiconductor field-effect transistors

Negative Bias Temperature Instability （NBTI） has become one of the most serious reliability problems of metaloxide-semiconductor field-effect transistors （MOSFETs）. The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H^＋ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H^＋ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H^＋ generated during NBTI stress.

Fabrication and Characterization of 1700 V 4H-SiC Vertical Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors

The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors （VDMOSFETs） are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance （Ron,sv） is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V （IDS 〈 lOOnA） at VGS = 0 V.

Interfacial and Electrical Properties of GaAs Metal-Oxide-Semiconductor Capacitor with ZrAlON as the Interfacial Passivation Layer

The ZrTiON gate-dielectric GaAs metal-oxide-semiconductor （MOS） capacitors with or without ZrAION as the interfacial passivation layer （IPL） are fabricated and their properties are investigated. The experimental results show that the GaAs MOS capacitor with the ZrAION IPL exhibits better interracial and electrical properties, including lower interface-state density （1.14 × 10^12 cm^-2eV^-1）, smaller gate leakage current （6.82 × 10^-5 A//cm^2 at Vfb ＋1V）, smaller capacitance equivalent thickness （1.5 nm）, and larger k value （26）. The involved mechanisms lie in the fact that the ZrAION IPL can effectively block the diffusion of Ti and O towards the GaAs surface, thus suppressing the formation of interracial Ga-/As-oxides and As-As dimers, which leads to improved interracial and electrical properties for the devices.

Performance of La203/InA1N/GaN metal-oxide-semiconductor high electron mobility transistors

We report on the performance of La203/InA1N/GaN metal-oxide-semiconductor high electron mobility transistors （MOSHEMTs） and InA1N/GaN high electron mobility transistors （HEMTs）. The MOSHEMT presents a maximum drain current of 961 mA/mm at Vgs = 4 V and a maximum transconductance of 130 mS/mm compared with 710 mA/mm at Vgs = 1 V and 131 mS/mm for the HEMT device, while the gate leakage current in the reverse direction could be reduced by four orders of magnitude. Compared with the HEMT device of a similar geometry, MOSHEMT presents a large gate voltage swing and negligible current collapse.

Experimental I-V and C-V Analysis of Schottky-Barrier Metal-Oxide-Semiconductor Field Effect Transistors with Epitaxial NiSi2 Contacts and Dopant Segregation

We present an experimental analysis of Schottky-barrier metal-oxide-semiconductor field effect transistors （SB- MOSFETs） fabricated on ultrathin body silicon-on-insulator substrates with a steep junction by the dopant implantation into the silicide process. The subthreshold swing of such SB-MOSFETs reaches 69mV/dec. Em- phasis is placed on the capacitance-voltage analysis of p-type SB-MOSFETs. According to the measurements of gate-to-source capacitance Cgs with respect to Vgs at various Vds, we find that a maximum occurs at the accumulation regime due to the most imbalanced charge distribution along the channel. At each Cgs peak, the difference between Vgs and Vds is equal to the Schottky barrier height （SBH） for NiSi2 on highly doped silicon, which indicates that the critical condition of channel pinching off is related with SBH for source/drain on chan- nel. The SBH for NiSi2 on highly doped silicon can affect the pinch-off voltage and the saturation current of SB-MOSFETs.

All-silicon carrier accumulation modulator based on a lateral metal-oxide-semiconductor capacitor

In silicon photonics, the carrier depletion scheme has been the most commonly used mechanism for demonstrat- ing high-speed electro-optic modulation. However, in terms of phase modulation efficiency, carrier- accumnlation-based devices potentially offer almost an order of carrier depletion. Previously reported accumulation modulator magnitude improvement over those based on designs only considered vertical metal-oxide- semiconductor （MOS） capacitors, which imposes serious restrictions on the design flexibility and integratability with other photonic components. In this work, for the first time to our knowledge, we report experimental demonstration of an all-silicon accumulation phase modulator based on a lateral MOS capacitor. Using a Mach-Zehnder interferometer modulator with a 500-μm-long phase shifter, we demonstrate high-speed modulation up to 25 Gbit/s with a modulation efficiency （V πLπ） of 1.53 V·cm.

Air-stable n-type transistors based on assembled aligned carbon nanotube arrays and their application in complementary metal-oxide-semiconductor electronics

Carbon nanotubes(CNTs)are ideal candidates for beyond-silicon nano-electronics because of their high mobility and low-cost processing.Recently,assembled massively aligned CNTs have emerged as an important platform for semiconductor electronics.However,realizing sophisticated complementary nano-electronics has been challenging due to the p-type nature of carbon nanotubes in air.Fabrication of n-type behavior field effect transistors(FETs)based on assembled aligned CNT arrays is needed for advanced CNT electronics.Here in this paper,we report a scalable process to make n-type behavior FETs based on assembled aligned CNT arrays.Air-stable and high-performance n-type behavior CNT FETs are achieved with high yield by combining the atomic layer deposition dielectric and metal contact engineering.We also systematically studied the contribution of metal contacts and atomic layer deposition passivation in determining the transistor polarity.Based on these experimental results,we report the successful demonstration of complementary metal-oxide-semiconductor inverters with good performance,which paves the way for realizing the promising future of carbon nanotube nano-electronics.

A CO_2 laser rapid-thermal-annealing SiO_x based metal-oxide-semiconductor light emitting diode

Enhanced near-infrared （NIR） electroluminescence （EL） of a metal-oxide-semiconductor light emitting device （MOSLED） made on CO2 laser-annealed SiOx film is demonstrated. An EL power of near 50 nW from CO2 laser rapid-thermal-annealing （RTA） MOSLED under a biased voltage of 85 V and a current density of 2.3 mA/cm^2 is preliminarily reported.

Review of semiconductor devices and other power electronics components at cryogenic temperature

With the increasing demand for high power density,and to meet extreme working conditions,research has been focused on inves-tigating the performance of power electronics devices at cryogenic temperatures.The aim of this paper is to review the performance of power semiconductor devices,passive components,gate drivers,sensors,and eventually power electronics converters at cryogenic temperatures.By comparing the physical properties of semiconductor materials and the electrical performance of commercial power semiconductor devices,silicon carbide switches show obvious disadvantages due to the increased on-resistance and switching time at cryogenic temperature.In contrast,silicon and gallium nitride devices exhibit improved performance when tem-perature is decreased.The performance ceiling of power semiconductor devices can be influenced by gate drivers,within which the commercial alternatives show deteriorated performance at cryogenic temperature compared to room temperature.Moreover,options for voltage and current sense in cryogenic environments are justified.Based on the cryogenic performance of the various components afore-discussed,this paper ends by presenting an overview of the published converter,which are either partially or fully tested in a cryogenic environment.

A High-Performance Silicon Electro-Optic Phase Modulator with a Triple MOS Capacitor

We propose and analyze a novel Si-based electro-optic modulator with an improved metal-oxide-semiconductor （MOS） capacitor configuration integrated into silicon-on-insulator （SOl）. Three gate-oxide layers embedded in the silicon waveguide constitute a triple MOS capacitor structure, which boosts the modulation efficiency compared with a single MOS capacitor. The simulation results demonstrate that the Vπ Lπ product is 2. 4V · cm. The rise time and fall time of the proposed device are calculated to be 80 and 40ps from the transient response curve, respectively,indicating a bandwidth of 8GHz. The phase shift efficiency and bandwidth can be enhanced by rib width scaling.

Neuronal signal detecting and stimulating circuit array for monolithic integrated MEA

A neuronal signal detecting circuit and a neuronal signal stimulating circuit designed for a monolithic integrated MEA（micro-electrode array） system are described. As a basic cell of the circuits, an OPA（ operational amplifier） is designed with low power, low noise, small size and high gain. The detecting circuit has a chip area of 290 μm × 400 μm, a power dissipation of 2.02 mW, an equivalent input noise of 17.72 nV/ Hz, a gain of 60. 5 dB, and an output voltage from - 2. 48 to ＋ 2. 5 V. The stimulating circuit has a chip area of 130 μm × 290 μm, a power dissipation of 740 μW, and an output voltage from - 2. 5 to 2. 04 V. The parameters show that two circuits are suitable for a monolithic integrated MEA system. The detecting circuit and MEA have been fabricated. The test results show that the detecting circuit works well.