A 10Gb/s GaAs PHEMT High Gain Preamplifier for Optical Receivers

A high gain cascade connected preamplifier for optical receivers is developed with 0.5μm GaAs PHEMT technology from the Nanjing Electronic Devices Institute. To begin with, the transimpedance amplifier has a -3dB bandwidth of 10GHz, with a small signal gain of around 9dB. The post-stage distributed amplifier （DA） has a -3dB bandwidth of close to 20GHz,with a small signal gain of around 12dB. As a whole,the cascade preamplifier has a measured small signal gain of 21.3dB and a transimpedance of 55.3dBΩ in a 50Ω system. With a higher signal-to-noise ratio than that of the TIA and a markedly improved waveform distortion compared with that of the DA, the measured output eye diagram for 10Gb/s NRZ pseudorandom binary sequence is clear and symmetric.

Relationship Between Noise Figure and Equivalent Input Noise Current Spectral Density for Optical Receiver Design

Based on the equivalent circuit model of a two-port optical receiver front-end,the relationship between the equivalent input noise current spectral density and the noise figure is analyzed. The derived relationship has universal validity for determining the equivalent input noise current spectral density for optical receiver designs, as verified by measuring a 155Mb/s high-impedance optical receiver front.end. Good agreement between calculated and simulated results has been achieved.

A 0.5mV High Sensitivity 200Mbps CMOS Limiting Amplifier with RSSI for Optical Receivers

A 0. 5mV high sensitivity,200Mbps CMOS limiting amplifier （LA） with 72dB ultra wide dynamic range is described. A novel active DC offset cancellation loop is elaborately analyzed and designed to achieve this performance. Using a signal path, a received signal strength indicator （RSSI）, based on the piecewise-linear approximation, is realized with a ± 2dB logarithmic accuracy in a 60dB indicating range. The architecture of the LA and RSSI employed is determined by the optimal sensitivity and RSSI accuracy for a specified speed, gain, and power consumption. It consumes 60mW from a single 5V supply. The active area is 1.05mm^2 using standard 5V 0.6μm CMOS technology.

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a tripleinductive transimpedance amplifier(TIA), direct current(DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers(VGA), and a reference-less clock and data recovery(CDR) circuit with built-in equalization technique. The TIA/VGA frontend measurement results demonstrate 72-dB? transimpedance gain, 20.4-GHz-3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10-12 BER at 26 Gb/s for a 2;-1 PRBS input with a-7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.

Switched-mode AGC circuits with internally created reset module for burst-mode unbalanced data optical receiver

This paper presents an innovative switched-mode auto gain control （AGC） circuit with internally created reset module for DC-10Mb/s burst-mode unbalanced （BMU） optical data transmission. Conventional AGC circuit is inappropriate for BMU data transmission because it is based on average level detection and requires considerable time to settle on a predefined gain. Therefore, we adopt a fast switched-mode AGC based on peak level detection. After the gain is adjusted, the peak level detectors need to re-detect the peak level of the input signal. Thus, we develop an internally created reset module. This AGC with reset module exhibits a fast operation and achieves an adjusted stable gain within one-bit, avoiding any bit loss up to 10Mb/s data rate. During power-up, the peak level detectors possibly hold an uncertain level resulting in the bit-errors. We propose a power-up reset circuit to solve this problem. Designed in a 0.5μm CMOS technology, the circuit achieves an optical sensitivity of better than -30dBm and a wide dynamic range of over 30dB with a power dissipation of only 30 mW from a 5V supply.

Concept and Design of a Novel High-Bandwidth,High-Sensitivity Differential Receiver for Optical Interconnections

A novel high-bandwidth, high-sensitivity differential optical receiver without any additional cost compared to general optical receivers, is proposed for high-speed optical communications and interconnections. High bandwidth and high sensitivity are achieved through a fully differential transimpedance amplifier with balanced input loads and two photodetectors to convert the incident light into a pair of differential photogenerated currents,respectively. In addition,a corresponding 0.35μm standard CMOS optoelectronic integrated receiver with two 60μm × 30μm, 1. 483pF fingered p^＋/n- well/p-substrate photodiodes is also presented. The simulation results demonstrate that it achieves a 1.37GHz bandwidth and a 81.9dBΩ transimpedance gain,supporting data rates up to at least 2Gbit/s. The device consumes a core area of 0. 198mm^2 and the optical sensitivity is at least - 13dBm for a 10^-12 bit error rate under a 2^15 - 1 PRBS input signal.

A 40 Gbit/s fully integrated optical receiver analog front-end in 90 nm CMOS

A fully integrated 40 Gbit/s optical receiver analog front-end （AFE） including a transimpedance amplifier （TIA） and a limiting amplifier （LA） for short distance communication is described in this paper. The proposed TIA employs a modified regulated cascode （RGC） configuration as input stage, and adopts a third order interleaving active feedback gain stage. The LA utilizes nested active feedback, negative capacitance, and inductor peaking technology to achieve high voltage gain and wide bandwidth. The tiny photo current received by the receiver AFE is amplified to a single-ended voltage swing of 200 mV（p-p）. Simulation results show that the receiver AFE provides conversion gain of up to 83 dBΩ and bandwidth of 34.7 GHz, and the equivalent input noise current integrated from 1 MHz to 30 GHz is about 6.6 μA（rms）.

High performance power-configurable preamplifier in a high-density parallel optical receiver

A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12 × 10 Gb/s high-density ultra-high speed parallel optical communication system. With critical limitations on power consumption, area and fabrication cost, the preamplifier achieves high performance, e.g. high bandwidth, high trans-impedance gain, low noise and high stability. A novel feed-forward common gate （FCG） stage is adopted to alleviate contradictions on trans-impedance gain and bandwidth by using a low headroom con- suming approach to isolate a large input capacitance and using complex pole peaking techniques to substitute induc- tors to achieve bandwidth extension. A multi-supply power-configurable scheme was employed to avoid wasteful power caused by a pessimistic estimation of process-voltage-temperature （PVT） variation. Two representative sam- ples provide a trans-impedance gain of 53.9 dBf2, a 3-dB bandwidth of 6.8 GHz, a power dissipation of 6.26 mW without power-configuration and a trans-impedance gain of 52.1 dBg2, a 3-dB bandwidth of 8.1 GHz, a power dis- sipation of 6.35 mW with power-configuration, respectively. The measured average input-referred noise-current spectral density is no more than 28 pA/√Hz. The chip area is only 0.08 x 0.08 mm2.

A 1.5Gb/s monolithically integrated optical receiver in the standard CMOS process

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10-9. The chip dissipates 60 mW under a single 3.3 V supply.

A monolithic,standard CMOS,fully differential optical receiver with an integrated MSM photodetector

This paper presents a realization of a silicon-based standard CMOS,fully differential optoelectronic integrated receiver based on a metal–semiconductor–metal light detector（MSM photodetector）.In the optical receiver, two MSM photodetectors are integrated to convert the incident light signal into a pair of fully differential photogenerated currents.The optoelectronic integrated receiver was designed and implemented in a chartered 0.35μm, 3.3 V standard CMOS process.For 850 nm wavelength,it achieves a 1 GHz 3 dB bandwidth due to the MSM photodetector’s low capacitance and high intrinsic bandwidth.In addition,it has a transimpedance gain of 98.75 dBΩ, and an equivalent input integrated referred noise current of 283 nA from 1 Hz up to–3 dB frequency.

Influence of the nonlinear phase and ASE noise on DPSK balanced optical receiver in optical fiber communication system

The analytical expression of bit error probability in a balanced differential phase-shift keying(DPSK) optical receiver considering nonlinear phase noise and EDFA ASE noise is given,which is very useful to estimate the performance of DPSK balanced and unbalanced receiver in optical communication system.Through analysis,if only nonlinear phase noise is considered,both the balance and unbalanced receivers have the same performances.But if adding the ASE noise of EDFA,the balanced receiver is better.

The 8×10 GHz Receiver Optical Subassembly Based on Silica Hybrid Integration Technology for Data Center Interconnection

An 8×10 GHz receiver optical sub-assembly （ROSA） consisting of an 8-channel arrayed waveguide grating （AWG） and an 8-channel PIN photodetector （PD） array is designed and fabricated based on silica hybrid integration technology. Multimode output waveguides in the silica AWG with 2% refractive index difference are used to obtain fiat-top spectra. The output waveguide facet is polished to 45° bevel to change the light propagation direction into the mesa-type PIN PD, which simplifies the packaging process. The experimentM results show that the single channel I dB bandwidth of AWG ranges from 2.12nm to 3.06nm, the ROSA responsivity ranges from 0.097 A/W to 0.158A/W, and the 3dB bandwidth is up to 11 GHz. It is promising to be applied in the eight-lane WDM transmission system in data center interconnection.

Design of Si-bipolar Monolithic Main Amplifier IC for Optical Fiber Receivers

A broadband amplifier with transadmittance and transimpedance stages is designed and two types of improved AGC amplifiers are developed on the base of theory study. Making use of the basic amplifier cells, a main amplifier IC for optical-fiber receivers is deliberated. By computer simulating the performances of the designed main amplifier meet the necessity of high gain and wide dynamic range . They are maximum voltage gain of 42 dB, the bandwidth of 730 MHz,the input signal( V p-p )range from 5 mV to 1 V,the output amplitude about 1 V, the dynamic range of 46 dB. The designed circuit containing no inductance and large capacitance will be convenient for realizing integration. A monolithic integrated design of 622 Mb/s main amplifier is completed.

A 58-dBΩ20-Gb/s inverter-based cascode transimpedance amplifier for optical communications

This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process.Multiple bandwidth enhancement techniques,including input bonding wire,input series on-chip inductive peak-ing and negative capacitance compensation,are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device,achieving an overall bandwidth enhancement ratio of 8.5.The electrical measure-ment shows TIA achieves 58 dBΩup to 12.7 GHz with a 180-fF off-chip photodetector.The optical measurement demonstrates a clear open eye of 20 Gb/s.The TIA dissipates 4 mW from a 1.2-V supply voltage.

Equivalent Noise Models in Fiber Optical Communication Systems

An equivalent noise model of optical receiver amplifiers as shown in Fig.1 has been given in many fiber optical communication literatures. It is proved in this paper that this equivalent noise model is neither equivalent to the original one nor measurable. The main reason is that the position of the input impedance in this noise model is not the same with its in the typical noise model,but the same S vn , S in with the typical noise model are used. So the equivalent noise model above is wrong and is not fit to be taken into application.

4×112 Gb/s hybrid integrated silicon receiver based on photonic-electronic co-design

A 4×112 Gb/s hybrid-integrated optical receiver is demonstrated based on the silicon-photonic vertical p-i-n photodetector and silicon–germanium transimpedance amplifier.We propose a photonic-electronic co-design technique to optimize both the device-level and system-level performance,based on the end-to-end equivalent circuit model of the receiver.Continuous-time linear equalization and shunt peaking are employed to enhance the frequency response.Experimental results reveal that the optical-to-electrical 3-dB bandwidth of the receiver is 48 GHz.Clear open NRZ eye diagrams at56 Gb/s and PAM-4 eye diagrams at 112 Gb/s are achieved without an equalizer in the oscilloscope.The measured bit error rates for 56 Gb/s in NRZ and 112 Gb/s in PAM-4 reach 1×10^(-12)and 2.4×10^(-4)(KP4-FEC:forward error correction)thresholds under-4 dBm input power,respectively.Furthermore,the proposed receiver boasts a power consumption of approximately2.2 pJ/bit,indicating an energy efficient solution for data center traffic growth.

A 12 Gbit/s limiting amplifier using 2 GaAs HBT technology for fiber-optic transmission system

A 12 Gbit/s limiting amplifier for fiber-optic transmission system is realized in a 2μm GaAs HBT technology. The whole circuit consists of an input buffer, three similar amplifier cells, an output buffer for driving 50 ft transmission lines and a pair of feedback networks for offset cancellation. At a positive supply voltage of 2 V and a negative supply voltage of - 2V, the power dissipation is about 280 mW. The small-signal gain is higher than 46 dB and the input dynamic range is about 40 dB with a constant single-ended output voltage swing of 400 mV. Satisfactory eye-diagrams are obtained at the bit rate of 12 Gbit/s limited by the test set-up. The chip area is 1.15 mm ×0.7 mm.

12Gb/s 0.25μm CMOS Low-Power 1∶4 Demultiplexer

A low power 12Gb/s single-stage 1 ： 4 demultiplexer （DEMUX） applied in SONET OC-192 is realized in TSMC＇s mix-signal 0. 25μm CMOS. All of the circuits are in source coupled FET logic （SCFL） to achieve as high a speed as possible and suppress common mode distortions. This DEMUX is featured for achieving singlestage demultiplexing by using a quarter-rate IQ clock. This method not only reduces the components of the DEMUX but also lowers its power dissipation. The fabricated DEMUX operates error free at 12Gb/s by 231 - 1 pseudorandom bit sequences in on-wafer testing. The chip size is 0. 9mm × 0.9mm and the power dissipation is only 210mW with a single 2.5V supply.

10 Gbit/s 0.25μm CMOS 1∶4 demultiplexer

A 10 Gbit/s (STM-64, OC-192) 1:4 demultiplexer (DEMUX) with 4-phase clock wasachieved in TSMC's standard 0.25 μm complementary metal-oxide-semiconductor (CMOS) technique. Allof the circuits are in source coupled FET logic (SCFL) to achieve as high as possible speed andsuppress common mode distortions. This DEMUX is featured by constant-delay buffers to generate a4-phase clock and adjust skews of the four channel outputs. The fabricated DEMUX operates error freeat 10 Gbit/s by 2^(31) -1 pseudorandom bit sequences (PRBS) via on-wafer testing. The measured rootmean square (rms) jitter, rising and failing edge of the eye-diagram are 11, 123 and 137 ps,respectively. The chip size is 0.9 mm x 1.2 mm and the power dissipation is 550 mW with a 3. 3 Vsupply.

4 × 20 GHz silica-based AWG hybrid integrated receiver optical sub-assemblies

Both the 4 × 20 GHz coarse wavelength division multiplexing and LAN-WDM receiver optical sub-assemblies（ROSAs） were developed. The ROSA package was hybrid integrated with a planar lightwave circuit arrayed waveguide grating（AWG） with 2% refractive index difference and a four-channel top-illuminated positive-intrinsicnegative photodetector（PD） array. The output waveguides of the AWG were designed in a multimode structure to provide flat-top optical spectra, and their end facet was angle-polished to form a total internal reflection interface to realize vertical coupling with a PD array. The maximum responsivity of ROSA was about 0.4 A/W, and its 3 dB bandwidth of frequency response was up to 20 GHz for each transmission lane. The hybrid integrated ROSA would be a cost-effective and easy-assembling solution for 100 Gb E data center interconnections.