The improved current-doubler-rectifier zero-voltage-switching PWM full-bridge converter (CDR ZVS PWM FB converter) achieves ZVS for the switches in a wide load range with the use of the energy stored in the output fil...The improved current-doubler-rectifier zero-voltage-switching PWM full-bridge converter (CDR ZVS PWM FB converter) achieves ZVS for the switches in a wide load range with the use of the energy stored in the output filter inductances, and the rectifier diodes commute naturally, therefore no oscillation and voltage spike occurs. The transformer needs no special manufacture method to limit the leakage inductance. The ZVS achievement and the design considerations for the output filter inductances and the blocking capacitor are discussed for the improved CDR ZVS PWM FB converter. A 540 W prototype converter is built in the lab to verify the operational principle and design considerations for the improved converter, the experimental results are also included.展开更多
A buck DC/DC switching regulator is implemented by automatically altering the modulation mode according to the load current that ranges from 0.01 to 3A. The pseudo-PFM mode is applied when duty cycle is less than 20% ...A buck DC/DC switching regulator is implemented by automatically altering the modulation mode according to the load current that ranges from 0.01 to 3A. The pseudo-PFM mode is applied when duty cycle is less than 20% ,and the PWM mode is selected in a range of duty cycle from 20% to 100%. The average conversion efficiency of the regulator is about 90% when the output current varies. The proposed dual-mode-control die is implemented in a 0.5μm DPDM CMOS mixed-signal process and a power p-MOSFET is used in the chip by hybrid integration.展开更多
A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented. The power solution involves a DC-DC buck converter and a followed low-dropout regulator （LDO）. The pulsewidth-modulation ...A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented. The power solution involves a DC-DC buck converter and a followed low-dropout regulator （LDO）. The pulsewidth-modulation （PWM） control method is adopted for better noise performance. An improved low-power highfrequency PWM control circuit is proposed, which halves the average quiescent current of the buck converter to 80 μA by periodically shutting down the OTA. The size of the output stage has also been optimized to achieve high efficiency under a light load condition. In addition, a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current. Fabricated with commercial 180-nm CMOS technology, the DC-DC converter achieves a peak efficiency of 93.1% under a 2 MHz working frequency. The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.展开更多
文摘The improved current-doubler-rectifier zero-voltage-switching PWM full-bridge converter (CDR ZVS PWM FB converter) achieves ZVS for the switches in a wide load range with the use of the energy stored in the output filter inductances, and the rectifier diodes commute naturally, therefore no oscillation and voltage spike occurs. The transformer needs no special manufacture method to limit the leakage inductance. The ZVS achievement and the design considerations for the output filter inductances and the blocking capacitor are discussed for the improved CDR ZVS PWM FB converter. A 540 W prototype converter is built in the lab to verify the operational principle and design considerations for the improved converter, the experimental results are also included.
文摘A buck DC/DC switching regulator is implemented by automatically altering the modulation mode according to the load current that ranges from 0.01 to 3A. The pseudo-PFM mode is applied when duty cycle is less than 20% ,and the PWM mode is selected in a range of duty cycle from 20% to 100%. The average conversion efficiency of the regulator is about 90% when the output current varies. The proposed dual-mode-control die is implemented in a 0.5μm DPDM CMOS mixed-signal process and a power p-MOSFET is used in the chip by hybrid integration.
文摘A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented. The power solution involves a DC-DC buck converter and a followed low-dropout regulator （LDO）. The pulsewidth-modulation （PWM） control method is adopted for better noise performance. An improved low-power highfrequency PWM control circuit is proposed, which halves the average quiescent current of the buck converter to 80 μA by periodically shutting down the OTA. The size of the output stage has also been optimized to achieve high efficiency under a light load condition. In addition, a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current. Fabricated with commercial 180-nm CMOS technology, the DC-DC converter achieves a peak efficiency of 93.1% under a 2 MHz working frequency. The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.
