Enhanced gated-diode-triggered silicon-controlled rectifier for robust electrostatic discharge (ESD) protection applications

A robust electron device called the enhanced gated-diode-triggered silicon-controlled rectifier (EGDTSCR) for electrostatic discharge (ESD) protection applications has been proposed and implemented in a 0.18-μm 5-V/24-V BCD process. The proposed EGDTSCR is constructed by adding two gated diodes into a conventional ESD device called the modified lateral silicon-controlled rectifier (MLSCR). With the shunting effect of the surface gated diode path, the proposed EGDTSCR, with a width of 50 μm, exhibits a higher failure current (i.e., 3.82 A) as well as a higher holding voltage (i.e., 10.21 V) than the MLSCR.

Enhancement of holding voltage by a modified low-voltage trigger silicon-controlled rectifier structure for electrostatic discharge protection

A novel structure of low-voltage trigger silicon-controlled rectifiers(LVTSCRs) with low trigger voltage and high holding voltage is proposed for electrostatic discharge(ESD) protection. The proposed ESD protection device possesses an ESD implant and a floating structure. This improvement enhances the current discharge capability of the gate-grounded NMOS and weakens the current gain of the silicon-controlled rectifier current path. According to the simulation results, the proposed device retains a low trigger voltage characteristic of LVTSCRs and simultaneously increases the holding voltage to 5.53 V, providing an effective way to meet the ESD protection requirement of the 5 V CMOS process.

Holding-voltage drift of a silicon-controlled rectifier with different film thicknesses in silicon-on-insulator technology

This paper presents a new phenomenon,where the holding-voltage of a silicon-controlled rectifier acts as an electrostatic-discharge protection drift in diverse film thicknesses in silicon-on-insulator（SOI） technology. The phenomenon was demonstrated through fabricated chips in 0.18μm SOI technology.The drift of the holding voltage was then simulated,and its mechanism is discussed comprehensively through ISE TCAD simulations.

Science Letters:A robust polysilicon-assisted SCR in ESD protection application

A novel polysilicon-assisted silicon-controlled rectifier （SCR） is presented and analyzed in this paper, which is fabricated in HHNEC＇s 0.18μm EEPROM process. The polysilicon-assisted SCRs take advantage of polysilicon layer to help bypass electro-static discharge （E S D） current without occupying extra layout area. TLP current-voltage （I-V） measurement results show that given the same layout areas, robustness performance of polysilicon-assisted SCRs can be improved to 3 times of conventional MLSCR＇s. Moreover, one-finger such polysilicon-assisted SCRs, which occupy only 947 [3mz layout area, can undergo 7-kV HBM ESD stress. Results further demonstrate that the S-type I-V characteristics of polysilicon-assisted SCRs are adjustable to different operating conditions by changing the device dimensions. Compared with traditional SCRs, this new SCR can bypass more ESD currents and consumes smaller IC area.

New DDSCR structure with high holding voltage for robust ESD applications

A novel dual direction silicon-controlled rectifier(DDSCR)with an additional P-type doping and gate(APGDDSCR)is proposed and demonstrated.Compared with the conventional low-voltage trigger DDSCR(LVTDDSCR)that has positive and negative holding voltages of 13.371 V and 14.038 V,respectively,the new DDSCR has high positive and negative holding voltages of 18.781 V and 18.912 V in a single finger device,respectively,and it exhibits suitable enough positive and negative holding voltages of 14.60 V and 14.319 V in a four-finger device for±12-V application.The failure current of APGDDSCR is almost the same as that of LVT-DDSCR in the single finger device,and the four-finger APGDDSCR can achieve positive and negative human-body model(HBM)protection capabilities of 22.281 kV and 23.45 kV,respectively,under 40-V voltage of core circuit failure,benefitting from the additional structure.The new structure can generate a snapback voltage on gate A to increase the current gain of the parasitic PNP in holding voltage.Thus,a sufficiently high holding voltage increased by the structure can ensure that a multi-finger device can also reach a sufficient holding voltage,it is equivalent to solving the non-uniform triggering problem of multi-finger device.The operating mechanism and the gate voltage are both discussed and verified in two-dimensional(2D)simulation and experiemnt.

Insight into multiple-triggering effect in DTSCRs for ESD protection

The diode-triggered silicon-controlled rectifier（DTSCR） is widely used for electrostatic discharge（ESD） protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigger/holding voltage, low parasitic capacitance. However, the multiple-triggering effect in the typical DTSCR device may cause undesirable larger overall trigger voltage, which results in a reduced ESD safe margin. In previous research, the major cause is attributed to the higher current level required in the intrinsic SCR. The related discussions indicate that it seems to result from the current division rule between the intrinsic and parasitic SCR formed in the triggering process. In this letter, inserting a large space into the trigger diodes is proposed to get a deeper insight into this issue. The triggering current is observed to be regularly reduced along with the increased space, which confirms that the current division is determined by the parasitic resistance distributed between the intrinsic and parasitic SCR paths. The theoretical analysis is well confirmed by device simulation and transmission line pulse（TLP） test results. The reduced overall trigger voltage is achieved in the modified DTSCR structures due to the comprehensive result of the parasitic resistance vs triggering current, which indicates a minimized multipletriggering effect.

A novel HBT trigger SCR in 0.35 μm SiGe BiCMOS technology

The silicon-controlled rectifier（SCR） device is known as an efficient electrostatic discharge（ESD） protection device due to the highest ESD robustness in the smallest layout area. However, SCR has some drawbacks,such as high trigger voltage and low holding voltage. In order to reduce the trigger voltage of the SCR device for ESD protection, a new heterojunction bipolar transistor（HBT） trigger silicon controlled rectifier（HTSCR） device in 0.35 m Si Ge Bi CMOS technology are proposed. The underlying physical mechanisms critical to the trigger voltage are demonstrated based on transmission line pulsing（TLP） measurement and physics-based simulation results. The simulation results prove that the trigger voltage of the HTSCR is decided by the collector-to-emitter breakdown voltage of the HBT structure in floating base configuration. The ESD experiment test results demonstrate the HTSCR can offer superior performance with a small trigger voltage, an adjustable holding voltage and a high ESD robustness. In comparison to the conventional MLSCR, the trigger voltage of the fabricated HTSCR can reduce to less than 50% of that of the MLSCR, and the I_（t2） of the HBT trigger SCR is 80% more than that of the MLSCR.