Design and Fabrication of Thermo-Optic 4×4 Switching Matrix in Silicon-on-Insulator

A rearrangeable nonblocking thermo-optic 4×4 switching matrix,which consists of five 2×2 multimode interference-based Mach-Zehnder interferometer(MMI-MZI) switch elements,is designed and fabricated.The minimum and maximum excess loss for the matrix are 6.6 and 10.4dB,respectively.The crosstalk in the matrix is measured to be between -12 and -19.8dB.The switching speed of the matrix is less than 30μs.The power consumption for the single switch element is about 330mW.

Fabrication and Evaluation of Bragg Gratings on Optimally Designed Silicon-on-Insulator Rib Waveguides Using Electron-Beam Lithography

The fabrication of Bragg gratings on silicon-on-insulator （SOI） rib waveguides using electron-beam lithography is presented. The grating waveguide is optimally designed for actual photonic integration. Experimental and theoretical evaluations of the Bragg grating are demonstrated. By thinning the SOl device layer and deeply etching the Bragg grating, a large grating coupling coefficient of 30cm^-1 is obtained.

New Method of Total Ionizing Dose Compact Modeling in Partially Depleted Silicon-on-Insulator MOSFETs

On the basis of a detailed discussion of the development of total ionizing dose （TID） effect model, a new commercial-model-independent TID modeling approach for partially depleted silicon-on-insulator metal-oxide- semiconductor field effect transistors is developed. An exponential approximation is proposed to simplify the trap charge calculation. Irradiation experiments with 60Co gamma rays for IO and core devices are performed to validate the simulation results. An excellent agreement of measurement with the simulation results is observed.

Analysis of single-event transient sensitivity in fully depleted silicon-on-insulator MOSFETs

Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28-nm technology and 0.2-lm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.

Study on the defect-related emissions in the light self-ion-implanted Si films by a silicon-on-insulator structure

This paper reports that the Si＋ self-ion-implantation are conducted on the silicon-on-insulator wafers with the 2SSi＋ doses of 7 ×1012, 1 × 1013, 4 × 1013, and 3× 1014 cm-2, respectively. After the suitable annealing, these samples are characterized by using the photoluminescence technique at different recorded temperatures. Plentiful emission peaks are observed in these implanted silicon-on-insulator samples, including the unwonted intense P~ band which exhibits a great potential in the optoelectronic application. These results indicate that severe transformation of the interstitial clusters can be manipulated by the implanting dose at suitable annealing temperatures. The high critical temperatures for the photoluminescence intensity growth of the two signatures are well discussed based on the thermal ionization model of free exciton.

Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology

In this paper, the effect of floating body effect （FBE） on a single event transient generation mechanism in fully depleted （FD） silicon-on-insulator （SOI） technology is investigated using three-dimensional technology computer-aided design （3D- TCAD） numerical simulation. The results indicate that the main SET generation mechanism is not carder drift/diffusion but floating body effect （FBE） whether for positive or negative channel metal oxide semiconductor （PMOS or NMOS）. Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking （IS） layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout.

Total dose radiation response of modified commercial silicon-on-insulator materials with nitrogen implanted buried oxide

Nitrogen ions of various doses are implanted into the buried oxide （BOX） of commercial silicon-on-insulator （SOI） materials, and subsequent annealings are carried out at various temperatures. The total dose radiation responses of the nitrogen-implanted SOI wafers are characterized by the high frequency capacitance-voltage （C-V） technique after irradi- ation using a Co-60 source. It is found that there exist relatively complex relationships between the radiation hardness of the nitrogen implanted BOX and the nitrogen implantation dose at different irradiation doses. The experimental results also suggest that a lower dose nitrogen implantation and a higher post-implantation annealing temperature are suitable for improving the radiation hardness of SOI wafer. Based on the measured C V data, secondary ion mass spectrometry （SIMS）, and Fourier transform infrared （FTIR） spectroscopy, the total dose responses of the nitrogen-implanted SOI wafers are discussed.

Improvement of total-dose irradiation hardness of silicon-on-insulator materials by modifying the buried oxide layer with ion implantation

The hardening of the buried oxide （BOX） layer of separation by implanted oxygen （SIMOX） silicon-on-insulator （SOI） wafers against total-dose irradiation was investigated by implanting ions into the BOX layers. The tolerance to total-dose irradiation of the BOX layers was characterized by the comparison of the transfer characteristics of SOI NMOS transistors before and after irradiation to a total dose of 2.7 Mrad（SiO2）. The experimental results show that the implantation of silicon ions into the BOX layer can improve the tolerance of the BOX layers to total-dose irradiation. The investigation of the mechanism of the improvement suggests that the deep electron traps introduced by silicon implantation play an important role in the remarkable improvement in radiation hardness of SIMOX SOI wafers.

Design and Fabrication of MEMS Gyroscopes on the Silicon-on-insulator Substrate with Decoupled Oscillation Modes

The mode coupling is a major factor to affect the precision of the micro electromechanical systems（MEMS） gyroscope. Currently, many MEMS gyroscopes with separate oscillation modes for drive and detection have been developed to decrease the mode coupling, but the gyroscope accuracy can not satisfy the high-precision demand well. Therefore, high performance decoupled MEMS gyroscopes is still a hot topic at present. An innovative design scheme for a MEMS gyroscope is designed, and in this design, the inertial mass is divided into three parts including the inner mass, the outer mass and the main frame mass. The masses are supported and separated by a set of mutually orthogonal beams to decouple their movements. Moreover, the design is modelled by multi-port-element network（MuPEN） method and the simulation results show that the mode coupling of the gyroscope between driving and sensing mode was eliminated effectively. Furthermore, we proposed a new silicon-on-insulator（SOI） process to fabricate the gyroscope. The scale factor of the fabricated gyroscope is 8.9 mV/（（~）os） and the quality factor（Q-factor） is as high as 600 at atmosphere pressure, and then, the resonant frequency, scale factor and bias drift has been test. Process and test results show that the proposed MEMS gyroscope are effective for decrease mode coupling, furthermore, it can achieve a high performance at atmosphere pressure. Furthermore, the MEMS gyroscope can achieve a high performance at atmosphere pressure. The research can be taken as good advice for the design and fabrication of MEMS gyroscope, meanwhile, it also provides technical support for speeding up of MEMS gyroscope industrialization.

Early effect modeling of silicon-on-insulator SiGe heterojunction bipolar transistors

Silicon germanium （SiGe） heterojunction bipolar transistor （HBT） on thin silicon-on-insulator （SOI） has recently been demonstrated and integrated into the latest SOI BiCMOS technology. The Early effect of the SOI SiGe HBT is analysed considering vertical and horizontal collector depletion, which is different from that of a bulk counterpart. A new compact formula of the Early voltage is presented and validated by an ISE TCAD simulation. The Early voltage shows a kink with the increase of the reverse base-collector bias. Large differences are observed between SOI devices and their bulk counterparts. The presented Early effect model can be employed for a fast evaluation of the Early voltage and is useful to the design, the simulation and the fabrication of high performance SOI SiCe devices and circuits.

Substrate bias effects on collector resistance in SiGe heterojunction bipolar transistors on thin film silicon-on-insulator

An analytical expression for the co/lector resistance of a novel vertical SiGe heterojunction bipolar transistor （HBT） on thin film silicon-on-insulator （SOI） is obtained with the substrate bias effects being considered. The resistance is found to decrease slowly and then quickly and to have kinks with the increase of the substrate-collector bias, which is quite different from that of a conventional bulk HBT. The model is consistent with the simulation result and the reported data and is useful to the frequency characteristic design of 0.13 μtm millimeter-wave SiGe SOI BiCMOS devices.

Influence of nitrogen implantation into the buried oxide on the radiation hardness of silicon-on-insulator wafers

In order to improve the total-dose radiation hardness of the buried oxide of separation by implanted oxygen silicon- on-insulator wafers, nitrogen ions were implanted into the buried oxide with a dose of 1016 cm-2, and subsequent annealing was performed at 1100 ℃. The effect of annealing time on the radiation hardness of the nitrogen implanted wafers has been studied by the high frequency capacitance-voltage technique. The results suggest that the improvement of the radiation hardness of the wafers can be achieved through a shorter time annealing after nitrogen implantation. The nitrogen-implanted sample with the shortest annealing time 0.5 h shows the highest tolerance to total-dose radiation. In particular, for the 1.0 and 1.5 h annealing samples, both total dose responses were unusual. After 300-krad（Si） irradiation, both the shifts of capacitance-voltage curve reached a maximum, respectively, and then decreased with increasing total dose. In addition, the wafers were analysed by the Fourier transform infrared spectroscopy technique, and some useful results have been obtained.

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

An analytical model for a novel triple reduced surface field（RESURF） silicon-on-insulator（SOI） lateral doublediffused metal–oxide–semiconductor（LDMOS） field effect transistor with n-type top（N-top） layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional（2D） Poisson＇s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage（BV） is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer（Q_（ntop）） is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.

An analytical model for coplanar waveguide on silicon-on-insulator substrate with conformal mapping technique

In this paper, the authors present an analytical model for coplanar waveguide on silicon-on-insulator substrate. The four-element topological network and the conformal mapping technique are used to analyse the capacitance and the conductance of the sandwich substrate. The validity of the model is verified by the full-wave method and the experimental data. It is found that the inductance, the resistance, the capacitance and the conductance from the analytical model show they are in good agreement with the corresponding values extracted from experimental Sparameter until 10 GHz.

Total Ionizing Dose Response of Different Length Devices in 0.13μm Partially Depleted Silicon-on-Insulator Technology

An anomalous total dose effect that the long length device is more susceptible to total ionizing dose than the short one is observed with the 0.13？μm partially depleted silicon-on-insulator technology. The measured results and 3D technology computer aided design simulations demonstrate that the devices with different channel lengths may exhibit an enhanced reverse short channel effect after radiation. It is ascribed to that the halo or pocket implants introduced in processes results in non-uniform channel doping profiles along the device length and trapped charges in the shallow trench isolation regions.

Analysis and Simulation of S-shaped Waveguide in Silicon-on-insulator

The simulation and analysis of S-shaped waveguide bend are presented.Bend radius larger than 30 mm assures less than 0.5 dB radiation loss for a 4-μm-wide silicon-on-insulator waveguide bend with 2-μm etch depth.Intersection angle greater than 20° provides negligible crosstalk (<-30 dB) and very low insertion loss.Any reduction in bend radius and intersection angle is at the cost of the degradation of characteristics of bent waveguide and intersecting waveguide, respectively.

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage（〉 600 V） integrable silicon-on-insulator（SOI） trench-type lateral insulated gate bipolar transistor（LIGBT） with a reduced cell-pitch is proposed.The LIGBT features multiple trenches（MTs）：two oxide trenches in the drift region and a trench gate extended to the buried oxide（BOX）.Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field（RESURF） effect.Both increase the breakdown voltage（BV）.Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop（Von）.The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss（Eoff）.The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10？3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.

A device model for thin silicon-on-insulator SiGe heterojunction bipolar transistors with saturation effects

In this paper, we describe the saturation effect of a silicon germanium （SiGe） heterojunction bipolar transistor （HBT） fabricated on a thin silicon-on-insulator （SOI） with a step-by-step derivation of the model formulation. The collector injection width, the internal base-collector bias, and the hole density at the base-collector junction interface are analysed by considering the unique features of the internal and the external parts of the collector, as they are different from those of a bulk counterpart.

Design,fabrication and characterization of a high-performance microring resonator in silicon-on-insulator

A high-performance microring resonator in a silicon-on-insulator rib waveguide is realized by using the electron beam lithography followed by inductively coupled plasma etching. The design and the experimental realization of this device are presented in detail. In addition to improving relevant processes to minimize propagation loss, the coupling efficiency between the ring and the bus is carefully chosen to approach a critical coupling for high performance operating. We have measured a quality factor of 21,200 and an extinction ratio of 12.SdB at a resonant wavelength of 1549.32nm. Meanwhile, a low propagation loss of 0.89dB/mm in a curved waveguide with a bending radius of 40μm is demonstrated as well.

Resistivity and Radio-Frequency Properties of Two-Generation Trap-Rich Silicon-on-Insulator Substrates

Crystal morphologies and resistivity of polysilicon trap-rich layers of two-generation trap-rich silicon-on-insulator（TR-SOI） substrates are studied. It is found that the resistivity of the trap-rich layer of generation 2（TR-G2）is higher than that of generation 1（TR-G1）, although the crystal morphologies of the trap rich layers are the same. In addition, the rf performance of two-generation TR-SOI substrates is investigated by coplanar waveguide lines and inductors. The results show that both the rf loss and the second harmonic distortion of TR-G2 are smaller than those of TR-G1. These results can be attributed to the higher resistivity values of both the trap-rich layer and the high-resistivity silicon（HR-Si） substrate of TR-G2. Moreover, the rf performance of the TR-SOI substrate with thicker buried oxide is slightly better. The second harmonics of various TR-SOI substrates are simulated and evaluated with the harmonic quality factor model as well. It can be predicted that the TR-SOI substrate will see further improvement in rf performance if the resistivities of both the trap-rich layer and HR-Si substrate increase.