ADVANCED FREQUENCY-DIRECTED RUN-LENTH BASED CODING SCHEME ON TEST DATA COMPRESSION FOR SYSTEM-ON-CHIP

Test data compression and test resource partitioning （TRP） are essential to reduce the amount of test data in system-on-chip testing. A novel variable-to-variable-length compression codes is designed as advanced fre- quency-directed run-length （AFDR） codes. Different [rom frequency-directed run-length （FDR） codes, AFDR encodes both 0- and 1-runs and uses the same codes to the equal length runs. It also modifies the codes for 00 and 11 to improve the compression performance. Experimental results for ISCAS 89 benchmark circuits show that AFDR codes achieve higher compression ratio than FDR and other compression codes.

Random testing for system-level functional verification of system-on-chip

In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.

Single-event effects induced by medium-energy protons in 28 nm system-on-chip

Single-event effects(SEEs)induced by mediumenergy protons in a 28 nm system-on-chip(SoC)were investigated at the China Institute of Atomic Energy.An on-chip memory block was irradiated with 90 MeV and 70 MeV protons,respectively.Single-bit upset and multicell upset events were observed,and an uppermost number of nine upset cells were discovered in the 90 MeV proton irradiation test.The results indicate that the SEE sensitivities of the 28 nm SoC to the 90 MeV and 70 MeV protons were similar.Cosmic Ray Effects on Micro-Electronics Monte Carlo simulations were analyzed,and it demonstrates that protons can induce effects in a 28 nm SoC if their energies are greater than 1.4 MeV and that the lowest corresponding linear energy transfer was 0.142 MeV cm^2 mg^-1.The similarities and discrepancies of the SEEs induced by the 90 MeV and 70 MeV protons were analyzed.

Investigation of single event effect in 28-nm system-on-chip with multi patterns

Single event effects (SEEs) in a 28-nm system-on-chip (SoC) were assessed using heavy ion irradiations, and susceptibilities in different processor configurations with data accessing patterns were investigated. The patterns included the sole processor (SP) and asymmetric multiprocessing (AMP) patterns with static and dynamic data accessing. Single event upset (SEU) cross sections in static accessing can be more than twice as high as those of the dynamic accessing, and processor configuration pattern is not a critical factor for the SEU cross sections. Cross section interval of upset events was evaluated and the soft error rates in aerospace environment were predicted for the SoC. The tests also indicated that ultra-high linear energy transfer (LET) particle can cause exception currents in the 28-nm SoC, and some even are lower than the normal case.

A 130-nm ferroelectric nonvolatile system-on-chip for internet of things

IEEE J.Solid-State Circuits,2019,doi:10.1109/JSSC.2018.2884349Nonvolatile processor(NVP)is promising for energy-harvesting-powered internet-of-things(IoT)devices,owing to its unique capability to sustain computation progress over power outages.Recently.

Scheduling method based on virtual flattened architecture for Hierarchical system-on-chip

As the technology of IP-core-reused has been widely used, a lot of intellectual property （IP） cores have been embedded in different layers of system-on-chip （SOC）. Although the cycles of development and overhead are reduced by this method, it is a challenge to the SOC test. This paper proposes a scheduling method based on the virtual flattened architecture for hierarchical SOC, which breaks the hierarchical architecture to the virtual flattened one. Moreover, this method has more advantages compared with the traditional one, which tests the parent cores and child cores separately. Finally, the method is verified by the ITC＇02 benchmark, and gives good results that reduce the test time and overhead effectively.

Reconfigurable Ultrasonic Testing System Development Using Programmable Analog Front-End and Reconfigurable System-on-Chip Hardware

Ultrasonic testing systems have been extensively used in medical imaging and non-destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems portable and more adaptable to the test environments, this study presents a reconfigurable ultrasonic testing system (RUTS), which possesses dynamic reconfiguration capabilities. RUTS consists a fully programmable Analog Front-End (AFE), which facilitates beamforming and signal conditioning for variety of applications. RUTS AFE supports up to 8 transducers for phased-array implementation. Xilinx Zynq System-on-Chip (SoC) based Zedboard provides the back-end processing of RUTS. The powerful ARM embedded processor available within Zynq SoC manages the ultrasonic data acquisition/processing and overall system control, which makes RUTS a unique platform for the ultrasonic researchers to experiment and evaluate a wide range of real-time ultrasonic signal processing applications. This Linux-based system is utilized for ultra-sonic data compression implementation providing a versatile environment for further development of ultrasonic imaging and testing system. Furthermore, this study demonstrates the capabilities of RUTS by performing ultrasonic data acquisition and data compression in real-time. Thus, this reconfigurable system enables ultrasonic designers and researchers to efficiently prototype different experiments and to incorporate and analyze high performance ultrasonic signal and image processing algorithms.

Data Fusion with Genetic Algorithm Based Lifetime Prediction for Dependable Multi-Processor System-on-Chips

With the prevalence of big-data technology,intricate,nanoscale Multi-Processor System-on-Chips(MP-SoCs)have been used in various safety-critical applications.However,with no extra countermeasures taken,this widespread use of MP-SoCs can lead to an undesirable decrease in their dependability.This study presents a promising approach using a group of Embedded Instruments(EIs)inside a processor core for health monitoring.Multiple health monitoring datasets obtained from the employed EIs are sampled and collated via the implemented experiment and thereafter used for conducting its remaining useful lifetime prognostics.This enables MP-SoCs to undertake preventive self-repair,thus realizing a zero mean downtime system and ensuring improved dependability.In addition,a principal component analysis based algorithm is designed for realizing the EI data fusion.Subsequently,a genetic algorithm based degradation optimization is employed to create a lifetime prediction model with respect to the processor.

Review on the Usage of Synchronous and Asynchronous FIFOs in Digital Systems Design

First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implemented in different ways. FIFOs are used not only for the pipeline design within a processor, for the inter-processor communication networks, for example Network-on-Chips (NoCs), but also for the peripherals and the clock domain crossing at the whole SoC level. In this paper, we review the interface, the circuit implementation, and the various usages of FIFOs in various levels of the digital design. We can find that the usage of FIFOs could greatly facilitate the signal storage, signal decoupling, signal transfer, power domain separation and power domain crossing in digital systems. We hope that more attentions are paid to the usages of synchronous and asynchronous FIFOs and more sophististicated usages are discovered by the digital design communities.

三种SoC片上总线的分析与比较

随着以IP核复用为基础的SoC设计技术的发展,工业界及研究组织正积极从事相关IP互联标准方案的制定工作。本文介绍了目前SoC设计中常用的三种片上总线标准,即IBM公司的CoreConnect总线、ARM公司的AMBA总线和OCPIP组织的OCP总线,重点分析和比较了它们的特性,并针对它们不同的特点,阐述其合适的应用领域。

安全通信协议设计及其芯片化实现

数据采集终端通过无线互联网与主站系统进行数据传输时会遇到安全问题,文章提出了一种安全解决方案,该方案设计了一套轻量级安全通信协议,采用可集成安全通信协议硬件安全芯片并将该安全通信协议集成到硬件安全芯片中。数据采集终端在使用了该硬件安全芯片后,只需要进行少量的软件改造即可实现与主站系统的安全数据传输;同时,硬件集成的方式能够有效防止安全通信协议扩散。实验结果表明,该方案完全满足安全通信的功能要求,而且性能更好。

步进电机的单片机控制系统设计研究

在科技快速发展的背景下,现阶段应用的步进电机所配置的齿轮箱、直线运动执行装置等较为先进,能实现难度较大、复杂程度较高的线性运动,这使步进电机得到了广泛应用与快速发展。在步进电机控制系统中,单片机具有至关重要的作用,作为核心部件,其性能质量会对步进电机的整体性能质量造成直接影响。所以,为保证步进电机功能正常发挥,需要合理设计单机片控制系统。基于此,主要探究了步进电机的单片机控制系统设计,以期为相关人员提供参考。

生化微传感SOC片内嵌入ADC的设计与实现

首先根据生化微传感SOC的应用场合和微传感器的特点,选定CR SAR ADC作为片内嵌入类型;基于SOC的标准CMOS工艺实现和低功耗的设计目标,分别进行了电容阵列、比较器、开关阵列和SAR控制逻辑等组成单元全定制原理图、版图设计,实现了片内嵌入10位ADC的整体芯片.流片实测结果DNL、INL最大值分别为+/-1.0LSB、+/-1.5LSB,功耗仅为4.62mW,满足生化微传感SOC数据转换的片内嵌入要求.

基于SOC与触摸屏技术的硬笔书法练习设备的设计

在电子产品设计过程中要充分考虑系统自身特点,根据需要设计并解决各个功能模块。本课题依据系统在设计和使用中涉及的各种状态及数据,结合现代电子技术与数据处理技术,提出适合于该硬笔书法练习系统的解决方案,并基于硬件系统实现各模块的功能,证明了方案的正确性及可实现性。

特定应用片上网络的研究综述

特大规模集成电路技术的飞速发展,使得把大量的知识产权(Intellectual Property,IP)核集成到单一的芯片上形成的片上系统成为了今后微电子发展的主流趋势。片上系统面临着许多设计和制造问题,片上网络为解决片上系统的这些问题提供一种行之有效的方案。当前及今后的片上系统都主要面向特定应用或特定应用类,因此,片上网络也是面向特定应用的片上网络,对特定应用片上系统面临的问题、特定片上网络的提出、发展、和主要研究内容进行综述。

基于SoC芯片的嵌入式医学检测设备平台设计

本文将嵌入式系统应用于医学检测设备的开发中,设计了以SoC芯片为核心的嵌入式医学检测设备平台,介绍并探讨了其软硬件系统的基本原理、设计思想、实现方法,并在最后介绍了一个实用的例子。通过医学检测设备软硬件平台,可有效避免设备开发时的重复工作,减少系统的研发时间和成本,缩短推出新产品的时间。

Co-design for an SoC embedded network controller

With the development of Ethernet systems and the growing capacity of modem silicon technology, embedded communication networks are playing an increasingly important role in embedded and safety critical systems. Hardware/software co-design is a methodology for solving design problems in processor based embedded systems. In this work, we implemented a new 1-cycle pipeline microprocessor and a fast Ethemet transceiver and established a low cost, high performance embedded network controller, and designed a TCP/IP stack to access the Intemet. We discussed the hardware/software architecture in the forepart, and then the whole system-on-a-chip on Altera Stratix EP1S25F780C6 device. Using the FPGA environment and SmartBit tester, we tested the system＇s throughput. Our simulation results showed that the maximum throughput of Ethemet packets is up to 7 Mbps, that of UDP packets is up to 5.8 Mbps, and that of TCP packets is up to 3.4 Mbps, which showed that this embedded system can easily transmit basic voice and video signals through Ethemet, and that using only one chip can realize that many electronic devices access to the Intemet directly and get high performance.

A front-end automation tool supporting design, verification and reuse of SOC

This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.

REVIEW OF ADVANCED FPGA ARCHITECTURES AND TECHNOLOGIES

Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.

浅论嵌入式系统

介绍了嵌入式系统的概念、构成和特点,以及它的发展过程和应用领域。