Capacitor self-calibration technique used in time-interleaved successive approximation ADC

A capacitor self-calibration circuit used in a successive approximation analog-to-digital converter （SA-ADC） is presented. This capacitor self-calibration circuit can calibrate erroneous data and work with the ADC by adding an additional clock period. This circuit is used in a 10 bit 32 Msample/s time-interleaved SA- ADC. The chip is implemented with Chart 0. 25 μm 2. 5 V process and totally occupies an area of 1.4 mm× 1.3 mm. After calibration, the simulated signal-to-noise ratio （SNR） is 59. 586 1 dB and the spurious-free dynamic range （SFDR） is 70. 246 dB at 32 MHz. The measured signal-to-noise and distortion ratio （SINAD） is 44. 82 dB and the SFDR is 63. 760 4 dB when the ADC samples a 5.8 MHz sinusoid wave.

Design of a 20-Gsps 12-bit time-interleaved analog-to-digital conversion system

The time-interleaved analog-to-digital conversion(TIADC)technique is an effective method for increasing the sampling rate in a waveform digitization system.In this study,a 20-Gsps TIADC system was designed.A wide-bandwidth performance was achieved by optimizing the analog circuits,and a sufficient effective number of bits(ENOB)performance guaranteed using the perfect reconstruction algorithm for mismatch error correction.The proposed system was verified by tests,and the results indicated that a-3 dB bandwidth of 6 GHz and the ENOB performance of 8.7 bits at 1 GHz and 7.6 bits at6 GHz were successfully achieved.

SPLIT-ADC BASED DIGITAL BACKGROUND CALIBRATION FOR TIME-INTERLEAVED ADC

A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.

A Timing Skew Calibration Scheme in Time-Interleaved ADC

This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.

Adaptive blind gain correction of time-interleaved ADCs forwide-band communication applications

High spectral efficiency is essential in design of multimedia communication systems such as L-band mobile in addition to various requirements of transmission quality. Time-interleaved A/D converter （TI-ADC） is an effective candidate to implement wide-band ADC with relatively slow circuits accounting for digital spectrum management. However, practical performance of TI-ADC is largely limited because of mismatches between different channels originated from manufacturing process variations. In this paper, a blind adaptive method is proposed to correct gain mismatch errors in TI-ADC, and it is verified through simulations on a two-channel TI-ADC. In proposed method, gain mismatch error is estimated and corrected in an adaptive scheme. Proposed compensated T1-ADC architecture is structurally very simple and hence suitable for realiza- tion in integrated circuits. Besides, proposed digital compensation algorithm not only is computationally efficient but also provides an improvement of 32.7 dB in the performance of two-channel TI ADC.

Improved time-interleaved error feedback delta sigma modulator for digital transmitter application

Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter application is presented in this paper. Two TI-EF-DSMs are compared,one is a conventional directly implemented and the other is the improved. The processing speed of the proposed two-channel improved time-interleaved error feedback delta sigma modulator( ITI-EF-DSM) is higher than the conventional directly implemented TI-EF-DSM for shortened critical path. A digital transmitter based on the ITI-EF-DSM is implemented on field progrmmable gate array( FPGA). The long term evolution( LTE) signals with different bandwidths of 5 MHz,10 MHz and 20 MHz are used as the signal source to evaluate the transmitter. The achieved SNR is 41 dB for the 20 MHz LTE signal with the processing clock of only 184 MHz.

A new method of waveform digitization based on time-interleaved A/D conversion

Time interleaved analog-to-digital conversion （TIADC） based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch errors among different analog-to-digital conversion channels have been developed previously. To overcome the speed limi- tation in hardware design and to implement the mismatch correction algorithm in real time, this paper proposes a fully parallel correction algorithm. A 12-bit l-Gsps waveform digitizer with ENOB around 10.5 bit from 5 MHz to 200 MHz is implemented based on the real-time correction algorithm.

A 14-bit 200-MS/s time-interleaved ADC with sample-time error calibration

Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this paper.The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals.The detected sample-time error is corrected by a voltage-controlled sampling switch.The experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB,and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after calibration.The calibration convergence time is about 20000 sampling intervals.

A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling

A 10-bit 250-MSPS two-channel time-interleaved charge-domain（CD） pipelined analog-to-digital converter （ADC） is presented.MOS bucket-brigade device（BBD） based CD pipelined architecture is used to achieve low power consumption.An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter.A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability.The ADC achieves a spurious free dynamic range（SFDR） of 67.1 dB,signal-to-noise ratio （SNDR） of 55.1 dB for a 10.1 MHz input,and SFDR of 61.6 dB,SNDR of 52.6 dB for a 355 MHz input at full sampling rate.Differential nonlinearity（DNL） is ＋0.5/-0.4 LSB and integral nonlineariry（INL） is ＋0.8/-0.75 LSB.Fabricated in a 0.18-μm 1P6M CMOS process,the prototype 10-bit pipelined ADC occupies 1.8×1.3 mm2 of active die area,and consumes only 68 mW at 1.8 V supply.

An 8-bit 100-MS/s digital-to-skew converter embedded switch with a 200-ps range for time-interleaved sampling

A sampling switch with an embedded digital-to-skew converter(DSC) is presented.The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage.A similar bridged capacitors' charge sharing structure is used to minimize the area.The circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s.The power consumption is 430μW at maximum.The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs(TI-ADCs) with the proposed DSC switch's demonstration.This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.

A 10-bit 100-Msps low power time-interleaved ADC using OTA sharing

A high performance 10-bit 100-MS/s two-channel time-interleaved pipelined ADC is designed for intermediate frequency 3G receivers,and OTA is shared among the channels for low power dissipation.Offset mismatch, gain mismatch and time skew mismatch are overcome by OTA sharing,increasing the accuracy of each channel and global passive sampling respectively.The linearity deterioration caused by the charge injection of the output switch and the crosstalk of the off-switch capacitor is removed by modifying the clock signal arrangement.The total power consumption of the presented ADC is 70 mW from a 3.3-V power supply.Fabricated in a 180-nm CMOS process,the core of the prototype occupies an area of 2.5×1.5 mm;,achieving more than 70-dB spurious-free dynamic range and over 56-dB signal-to-noise distortion ratio over the Nyquist input band at 100-MHz sampling frequency.

A 14-bit 250-MS/s current-steering CMOS digital-to-analog converter

A 14-bit 250-MS/s current-steering digital-to-analog converter（DAC） was fabricated in a 0.13μm CMOS process.In conventional high-speed current-steering DACs,the spurious-free dynamic range（SFDR） is limited by nonlinear distortions in the code-dependent switching glitches.In this paper,the bottleneck is mitigated by the time-relaxed interleaving digital-random-return-to-zero（TRI-DRRZ）.Under 250-MS/s sampling rate,the measured SFDR is 86.2 dB at 5.5-MHz signal frequency and 77.8 dB up to 122 MHz.The DAC occupies an active area of 1.58 mm2 and consumes 226 mW from a mixed power supply of 1.2/2.5 V.

A 16 b 2 GHz digital-to-analog converter in 0.18 μm CMOS with digital calibration technology

This paper presents a 16-bit 2 GSPS digital-to-analog converter （DAC） in 0.18/zm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB ＆ INL less than ±4.3 LSB after the chip is calibrated.