A real-time calibration method based on time-to-digital converter for accelerator timing system

The high-intensity heavy-ion accelerator facility(HIAF)is a scientific research facility complex composed of multiple cas-cade accelerators of different types,which pose a scheduling problem for devices distributed over a certain range of 2 km,involving over a hundred devices.The white rabbit,a technology-enhancing Gigabit Ethernet,has shown the capability of scheduling distributed timing devices but still faces the challenge of obtaining real-time synchronization calibration param-eters with high precision.This study presents a calibration system based on a time-to-digital converter implemented on an ARM-based System-on-Chip(SoC).The system consists of four multi-sample delay lines,a bubble-proof encoder,an edge controller for managing data from different channels,and a highly effective calibration module that benefits from the SoC architecture.The performance was evaluated with an average RMS precision of 5.51 ps by measuring the time intervals from 0 to 24,000 ps with 120,000 data for every test.The design presented in this study refines the calibration precision of the HIAF timing system.This eliminates the errors caused by manual calibration without efficiency loss and provides data support for fault diagnosis.It can also be easily tailored or ported to other devices for specific applications and provides more space for developing timing systems for particle accelerators,such as white rabbits on HIAF.

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

A high-precision and 10 bit two-step Time-to-Digital Converter for TOF application

A two-step high-precision Time-to-Digital Converter(TDC),integrated with a Single-Photon Avalanche Diode(SPAD),used for Time-Of-Flight(TOF)application,has been developed and tested.Time interval measurement is performed by the coarse counter and fine interpolator,which are utilized to measure the total periods and the residue time of the reference clock,respectively.Following a detail analysis of time precision and clock jitter in the two-step structure,the prototype TDC fabricated in GSMC 1P6M 0.18μm CMOS Image Sensor(CIS)technology exhibits a Single-Shot Precision(SSP)of 11.415 ps and a dynamic range of 216.7 ns.In addition,a pixel of the chip occupies 100μm×100μm,and the measured Integral Nonlinearity(INL)and Differential Nonlinearity(DNL)are better than±0.88 LSB and±0.67 LSB,respectively.Meanwhile,the overall power consumption of the chip is 35 mW at 1.8 V power supply.Combined with these characteristics,the designed chip is suitable for TOF-based ranging applications.

PULSE SHRINKING TIME-TO-DIGITAL CONVERTER FOR UWB APPLICATION

A kind of architecture of Time-to-Digital Converter(TDC) for Ultra-WideBand(UWB) application is presented. The proposed TDC is based on pulse shrinking, and implemented in a Field Programmable Gate Array(FPGA) device. The pulse shrinking is realized in a loop containing two Programmable Delay Lines(PDLs) or a two-channel PDL. One line(channel) delays the rising edge and the other line(channel) delays the falling edge of a circulating pulse. Delay resolution of PDL is converted into a digital output code under known conditions of pulse width. This delay resolution measurement mechanism is different from the conventional time interval measurement mechanism based on pulse shrinking of conversion of unknown pulse width into a digital output code. This mechanism automatically avoids the influence of unwanted pulse shrinking by any circuit element apart from the lines. The achieved relative errors for four PDLs are within 0.80%–1.60%.

Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution

This paperpresents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13μm CMOS technology. The simulation results demonstrate a linear input-output characteristic for input dynamic range from 0 to 1.6ns with a time resolution of 25ps.

High Precision Absolute Gravity Meter Based on Time-to-Digital Conversion in FPGA

This paper proposes a novel method to design a high precision portable gravity acceleration meter on the Field Programmable Gate Array(FPGA)platform.Two technologies are used in FPGA to improve the time measurement accuracy to 54 ps and the measurement accuracy of g to the level of 1μGal(1 Gal=1 cm/s^(2)).The one is the proposed clock rising edge counting method for measuring the coarse time,in which the measured coarse time resolution can reach 5 ns by setting the clock frequency up to 200 MHz.The other is the realization of the time-to-digital conversion(TDC)circuits in FPGA which can further improve the time measurement accuracy to 54 ps.In the TDC circuit,we analyze the influence of the frequency stability of crystal oscillator and the distance of infrared tube on the measurement accuracy of g.The increase of frequency stability(10^(–9)to 10^(–11))can greatly improve the measurement accuracy of g(5.8143 to 2.0799μGal),but further increase of frequency stability(10^(–11)to 10^(–12))has little effect on improving the accuracy of g.Through analysis and simulation,it is found that the setting of distance between laser pair also has a great influence on the accuracy of g.Only when the distance is set to the optimal,we can make the accuracy of g the highest.In this paper,the method of obtaining the best distance and the corresponding accuracy of g are given.In addition,the proposed system uses Nios II soft core processor to implement all the controlling,calculation and display functions,which improves system integration,reduces system cost and meets the needs of field geological survey and gravity prospecting.

A multi-path gated ring oscillator based time-to-digital converter in 65 nm CMOS technology

A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2.The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm^2.According to the measurement results,the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range,the maximum clock frequency of this circuit is larger than 200 MHz.Under a 1 V power supply,with a 200-800 ps input time difference,the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.

Design of a 10 bit high resolution,high speed time-to-digital converter using a two-step pulse-train time amplifier

A high resolution and fast conversion rate time-to-digital converter （TDC） design based on time amplifier （TA） is proposed. The pulse-train TA employs a two-step scheme. The input time interval is first amplified by a N-times TA and the effective time is extracted in pulse-train using a time-register. Then the resulted interval is further amplified by the other pulse-train amplifier to obtain the final result. The two-step TA can thus achieve large gain that is critical for high resolution TDC. Simulation results in 1.2 V, 65 nm technology showed that for a 10 bit TDC, a resolution of 0. 8 ps and a conversion rate of 150 MS/s are achieved while consuming 2. 1 mW power consumption.

Design and implementation of GM- APD array readout circuit for infrared imaging

Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.

Readout electronics of a prototype time-of-flight ion composition analyzer for space plasma

Readout electronics is developed for a prototype time-of-flight(TOF) ion composition spectrometer for in situ measurement of the mass/charge distributions of major ion species from 200 to 100 ke V/e in space plasma.By utilizing a constant fraction discriminator(CFD) and time-to-digital converter(TDC), challenging dynamic range measurements were performed with high time resolution and event rates. CFD was employed to discriminate the TOF signals from the micro-channel plate and channel electron multipliers. TDC based on the combination of counter and OR-gate delay chain was designed in a highreliability flash field programmable gate array. Owing to the non-uniformity of the delay chain, a correction algorithm based on integral nonlinearity compensation was implemented to reduce the time uncertainty. The test results showed that the electronics achieved a low timingerror of < 200 ps in the input range from 35 to 500 m V for the CFD, and a time resolution of ～550 ps with time uncertainty < 180 ps after correction and a time range of6.4 ls for the TDC. The TOF spectrum from an electron beam experiment of the impacting N_2 gas further indicated the good performance of this readout electronic.

A time and charge measurement board for muon tomography of high-Z materials

In this paper, a versatile time and charge measurement(MQT) board for muon tomography is described in detail. For time measurement, the general-purpose timeto-digital converter(TDC) chip TDC-GP2 is employed,while for charge measurement, digitization plus numerical integration in field programmable gate array is employed.Electronic tests demonstrate that the total 32 channels of two MQT boards have a time resolution of superior than100 ps, with excellent linearity for time and charge measurement.

Error analysis and correction of high-accuracy modulation domain measurement

Modulation domain measurement can be u sed to analyze the frequency,phase,and time intervals which transiently change with time.During the implementation of modulation domain analyzer,meas urement errors can be introduced in multiple parts.Aiming at a typical implementation of modul ation domain analyzer,this paper analyzes the inherent error between channe l s,temperature drift error in time-to-digital converter(TDC),random err or,time-base error and their influence on the modulation domain measurement.It also gives a correction sche me and comparison of the measurement results.The frequency resolution can be im proved from 10 to 12 bit/s after correction.

TOT measurement implemented in FPGA TDC

Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays（FPGAs）, FPGA time-to-digital converters（TDCs） have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold（TOT） measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC＇s integrity.This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method,TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15 ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates.

A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA

A fast-locking all-digital delay-locked loop（ADDLL） is proposed for the DDR SDRAM controller interface in a field programmable gate array（FPGA）.The ADDLL performs a 90°phase-shift so that the data strobe（DQS） can enlarge the data valid window in order to minimize skew.In order to further reduce the locking time and to prevent the harmonic locking problem,a time-to-digital converter（TDC） is proposed.A duty cycle corrector（DCC） is also designed in the ADDLL to adjust the output duty cycle to 50%.The ADDLL,implemented in a commercial 0.13μm CMOS process,occupies a total of 0.017 mm^2 of active area.Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps.The time interval error（TIE） of the proposed circuit is 60.7 ps.