A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS

A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.

A 24−30 GHz 8-element dual-polarized 5G FR2 phased-array transceiver IC with 20.8-dBm TX OP1dB and 4.1-dB RX NF in 65-nm CMOS

This article presents an 8-element dual-polarized phased-array transceiver(TRX)front-end IC for millimeter-wave(mm-Wave)5G new radio(NR).Power enhancement technologies for power amplifiers(PA)in mm-Wave 5G phased-array TRX are discussed.A four-stage wideband high-power class-AB PA with distributed-active-transformer(DAT)power combining and multi-stage second-harmonic traps is proposed,ensuring the mitigated amplitude-to-phase(AM-PM)distortions across wide carrier frequencies without degrading transmitting(TX)power,gain and efficiency.TX and receiving(RX)switching is achieved by a matching network co-designed on-chip T/R switch.In each TRX element,6-bit 360°phase shifting and 6-bit 31.5-dB gain tuning are respectively achieved by the digital-controlled vector-modulated phase shifter(VMPS)and differential attenuator(ATT).Fabricated in 65-nm bulk complementary metal oxide semiconductor(CMOS),the proposed TRX demonstrates the measured peak TX/RX gains of 25.5/21.3 dB,covering the 24−29.5 GHz band.The measured peak TX OP1dB and power-added efficiency(PAE)are 20.8 dBm and 21.1%,respectively.The measured minimum RX NF is 4.1 dB.The TRX achieves an output power of 11.0−12.4 dBm and error vector magnitude(EVM)of 5%with 400-MHz 5G NR FR2 OFDM 64-QAM signals across 24−29.5 GHz,covering 3GPP 5G NR FR2 operating bands of n257,n258,and n261.

A 256 Gb/s electronic−photonic monolithically integrated transceiver in 45 nm CMOS

With the explosive development of artificial intelligence(AI),machine learning(ML),and high-performance comput-ing(HPC),the ever-growing data movement is asking for high density interconnects with higher bandwidth(BW),lower power and lower latency[1−3].The optical I/O leverages silicon photonic(SiPh)technology to enable high-density large-scale integrated photonics.

Implementation of a 6 GHz band TDD RF transceiver for the next generation mobile communication system

The development of a high performance wideband radio frequency （RF） transceiver used in the next generation mobile communication system is presented. The developed RF transceiver operates in the 6 to 6.3 GHz band and the channel bandwidth is up to 100 MHz. It operates in the time division duplex （TDD） mode and supports the multiple-input multipleoutput （MIMO） technique for the international mobile telecommunications （IMT）-advanced systems. The classical superheterodyne scheme is employed to achieve optimal performance. Design issues of the essential components such as low noise amplifier, power amplifier and local oscillators are described in detail. Measurement results show that the maximum linear output power of the RF transceiver is above 23 dBm, and the gain and noise figure of the low noise amplifier is around 24 dB and below 1 dB, respectively. Furthermore, the error vector magnitude （EVM） measurement shows that the performance of the developed RF transceiver is well beyond the requirements of the long term evolution （LTE）-advanced system. With up to 8 x 8 MIMO configuration, the RF transceiver supports more than a 1 Gbit/s data rate in field tests.

A Novel Digital Transceiver for CT0 Standard

This paper introduces a novel digital transceiver for the cordless telephone zero （CT0） standard,which uses a digital modulation and demodulation technique to handle the signal instead of the traditional analog meth-od. In the transmitter,a fractional-N phase locked loop （PLL） is utilized to realize the continuous phase frequency shift key （CPFSK） modulation,and a 2 Ts raised cosine （2RC） shaping technique is used to reduce the occupied bandwidth. In the receiver,a novel digital method is proposed to demodulate the 2RC CPFSK signal. This chip is fabricated using an SMIC 0.35μm mixed signal CMOS process with a die size of 2mm × 2mm. With an external low noise amplifier （LNA）,the sensitivity of the chip is better than -103dBm.

Low Voltage CMOS Gilbert Mixers for Bluetooth Transceiver

Based on the analyses of the reported Gilbert mixers operating at low supply vol tage,a down-conversion mixer and an up-conversion mixer for 2.4GHz bluetooth transceiver are presented with the modified low voltage design techniques,respe ctively.Feedback and current mirror techniques suitable for low voltage operatio n are used to improve the linearity of the up-conversion mixer,and folded-casc ode output stage is adopted to optimize the noise and conversion gain of the dow n-conversion mixer operating at low voltage.Based on 0.35μm CMOS technology,s imulations are performed with 2V supply voltage.The results show that 20dBm thir d-order intercept point (IIP3),87mV output signal amplitude are achieved for up -conversion mixer with about 3mA current;while 20dB conversion gain (CG),6.5nV /Hz input-referred noise,4.4dBm IIP3 are obtained for down-conversion mixer with about 3.5mA current.

Design and Test of a CMOS Low Noise Amplifier in Bluetooth Transceiver

A RF low noise amplifier,integrated in a single bluetooth transceiver chip and fabricated in 0.35μm digital CMOS technology,is presented.Under the consideration of ESD protection and package,design methodology is discussed from the aspects of noise optimization,impedance match,and forward gain.At 2.05GHz,the measured S 11 is -6.4dB, S 21 is 11dB with 3dB-BW of 300MHz,and NF is about 5.3dB.It indicates that comprehensive consideration of parasitics,package model,and reasonable process is necessary for RF circuit design.

CMOS Mixers for 2.4GHz WLAN Transceivers

A down-conversion mixer and an up-conversion mixer for 2.4GHz WLAN transceivers are presented.The down-conversion mixer uses a class-AB input stage to get high linearity and to realize input impedance matching and single-ended to differential conversion.The mixers are implemented in 0.18μm CMOS process.The measured results are given to show their performance.

A 2.4GHz CMOS Monolithic Transceiver Front-End for IEEE 802.11b Wireless LAN Applications

A 2. 4GHz CMOS monolithic transceiver front-end for IEEE 802. llb wireless LAN applications is presented. The receiver and transmitter are both of superheterodyne structure for good system performance. The frontend consists of five blocks., low noise amplifier,down-converter, up-converter, pre-amplifier, and LO buffer. Their input/output impedance are all on-chip matched to 50 Ω except the down-converter which has open-drain outputs. The transceiver RF front-end has been implemented in a 0. 18μm CMOS process. When the LNA and the down-converter are directly connected, the measured noise figure is 5.2dB, the measured available power gain 12. 5dB, the input l dB compression point --18dBm,and the third-order input intercept point --7dBm. The receiver front-end draws 13.6mA currents from the 1.8V power supply. When the up-converter and pre-amplifier are directly connected, the measured noise figure is 12.4dB, the power gain is 23. 8dB, the output ldB compression point is 1.5dBm, and the third-order output intercept point is 16dBm. The transmitter consumes 27.6mA current from the 1.8V power supply.

Joint Transceiver Designs for Full-Duplex MIMO SWIPT Systems Based on MSE Criterion

For the simultaneous wireless information and power transfer(SWIPT), the full-duplex MIMO system can achieve simultaneous transmission of information and energy more efficiently than the half-duplex. Based on the mean-square-error(MSE) criterion, the optimization problem of joint transceiver design with transmitting power constraint and energy harvesting constraint is formulated. Next, by semidefinite relaxation(SDR) and randomization method, the SDRbased scheme is proposed. In order to reduce the complexity, the closed-form scheme is presented with some simplified measures. Robust beamforming is then studied considering the practical condition. The simulation results such as MSE versus signal-noise-ratio(SNR), MSE versus the iteration number, well prove the performance of the proposed schemes for the system model.

Silicon photonic transceivers for application in data centers

Global data traffic is growing rapidly,and the demand for optoelectronic transceivers applied in data centers(DCs)is also increasing correspondingly.In this review,we first briefly introduce the development of optoelectronics transceivers in DCs,as well as the advantages of silicon photonic chips fabricated by complementary metal oxide semiconductor process.We also summarize the research on the main components in silicon photonic transceivers.In particular,quantum dot lasers have shown great potential as light sources for silicon photonic integration—whether to adopt bonding method or monolithic integration—thanks to their unique advantages over the conventional quantum-well counterparts.Some of the solutions for highspeed optical interconnection in DCs are then discussed.Among them,wavelength division multiplexing and four-level pulseamplitude modulation have been widely studied and applied.At present,the application of coherent optical communication technology has moved from the backbone network,to the metro network,and then to DCs.

Design of 60GHz RF Transceiver in CMOS:Challenges and Recent Advances

With more scaling, the speed of than 40 years Moore CMOS transistors is around 100 GHz. Such fact makes it possible to realize mm-wave circuits in CMOS. However, with the target of achieving broadband and power-efficient operation, 60 GHz CMOS RF transceiver faces severe challenges. After reviewing the technology issues, regarding the 60 GHz applications, this paper discusses design challenges both from the system and the building block levels, and also presents some simulated or measured circuits results.

Low Power Single-Chip RF Transceiver for Human Body Cormunication

Human body communication is proposed as a promising body proximal comanunication tech- nology for body sensor networks. To achieve low power and slmll volume ill the sensor nodes, a Ra-dio Frequency （RF） application-specific integrated circuit transceiver tbr Human Body Commnunication （HBC） is presented and the characteristics of HBC are investigated. A high data rate On-Off Keying （OOK）/Frequency-Shift Keying （FSK） modulation protocol and an OOK/FSK delrodulator circuit are introduced in this paper, with a data-rate-to-carrier-frequency ratio up to 70%. A low noise amplifier is proposed to handle the dynamic range problem and improve the sensitivity of the receiver path. In addi-tion, a low power autonmatic-gain-control system is realized using a novel architecture, thereby render-ing the peak detector circuit and loop filter unneces-sary. Finally, the complete chip is fabricated. Simula-tion results suggest receiver sensitivity to be-75 dBm. The transceiver shows an overall power con-smxption of 32 mW when data rate is 5 Mbps, de-livering a P1dB output power of - 30 dBm.

A 40 Gb/s SerDes Transceiver Chip with Controller and PHY in a 65 nm CMOS Technology

A 40 Gb/s full serializer and deserializer (SerDes) transceiver with controller and physical layer (PHY) is presented.The controller mainly contains protocol transmission, forward error correction and user layer build-in self-test (BIST).The physical coding sub-layer (PCS) provides the functions of 64/66 encoder/decoder, PHY BIST, and polarity control.In the physical medium attachment (PMA), both transmitter (TX) and receiver (RX) adopt quarter-rate architecture to relax the timing constraint and reduce power dissipation.The receiver utilizes the phase interpolator (PI) based clock and data recovery (CDR) with bang-bang phase detector (BBPD) to extract the synchronic clock for retiming and de-multiplexing.The multiple-MUX based 4-tap FFE and a two-stage cascade CTLE are employed to mitigate the inter-symbol interference (ISI).In addition, a proposed 4∶1 MUX is used to improve the output jitter performance and reduce the power consumption.Fabricated in a 65 nm CMOS technology, the full transceiver consumes 890 mW at 40 Gb/s and occupies 12 mm 2 .The measurement results show that this transceiver can achieve bit error rate (BER)< 10 -12 after a 15.3 dB loss channel at 20 GHz.

A compact transmit/receive switch for 2.4 GHz reader-less active RFID tag transceiver

Radio frequency identification(RFID) is a ubiquitous identification technology nowadays. An on-chip high-performance transmit/receive(T/R) switch is designed and simulated in 0.13-μm CMOS technology for reader-less RFID tag. The switch utilizes only the transistor width and length(W/L) optimization, proper gate bias resistor and resistive body floating technique and therefore,exhibits 1 d B insertion loss, 31.5 d B isolation and 29.2 d Bm 1-d B compression point(P1d B). Moreover, the switch dissipates only786.7 n W power for 1.8/0 V control voltages and is capable of switching in 794 fs. Above all, as there is no inductor or capacitor used in the circuit, the size of the switch is 0.00208 mm2 only. This switch will be appropriate for reader-less RFID tag transceiver front-end as well as other wireless transceivers operated at 2.4 GHz band.

A NOVEL PHYSICAL-LAYER TRANSCEIVER USED IN USB2.0 SERIAL DATA LINK

The paper proposes a novel transceiver in physical layer for high-speed serial data link based upon Universal Serial Bus (USB) 2.0, comprising transmitter and receiver. In the design, transmitter contains pre-and-main driver to satisfy slew rate of output data, receiver includes optimized topology to improve preci- sion of received data. The circuit simulation is based on Cadence’s spectre software and Taiwan Semiconduc- tor Manufacture Corporation’s library of 0.25μm mixed-signal Complementary Metal-Oxide Semiconductor (CMOS) model. The front and post-simulation results reveal that the transceiver designed can transmit and re- ceive high-speed data in 480Mbps, which is in agreement with USB2.0 specification. The chip of physi- cal-layer transceiver has been designed and implemented with 0.25μm standard CMOS technology.

Decoupled estimation of frequency-dependent IQI and channel for OFDM systems with direct-conversion transceivers

The in-phase and quadrature-phase imbalance (IQI) is one of the major radio frequency impairments existing in orthogonal frequency division multiplexing (OFDM) systems with direct-conversion transceivers. During the transmission of the communication signal, the impact of IQI is coupled with channel impulse responses (CIR), which makes the traditional channel estimation schemes ineffective. A decoupled estimation scheme is proposed to separately estimate the frequency-dependent IQI and wireless channel. Firstly, the generalized channel model is built to separate the parameters of IQI and wireless channel. Then an iterative estimation scheme of frequency-dependent IQI is designed at the initial stage of communication. Finally, based on the estimation result of IQI, the least square algorithm is utilized to estimate the channel-related parameters at each time of channel variation. Compared with the joint estimation schemes of IQI and channel, the proposed decoupled estimation scheme requires much lower training overhead at each time of channel variation. Simulation results demonstrate the good estimation performance of the proposed scheme.

Mathematical Formulations of Signal Propagation in Ultra-Wideband Transceiver Systems under a UWB Channel Environment with an Extension of Frequency Offset Correction

This paper analyzes mathematically the crucial aspects of signal processing in a Multi-Band (MB) Orthogonal Frequency Division Multiplexing (OFDM) based system considering Ultra-Wideband (UWB) channel environment. In the process of analysis, it emphasizes the significant features of UWB receiver design in comparison with ‘conventional’ narrow-band system. The analysis shows that the high dispersive nature of a frequency selective UWB channel effects the design of different signal processing blocks like pre-select filter, low noise amplifier (LNA) and analog-to-digital (A/D) converter in the receiver front end. The characteristic functions of each of these stages are now dominated by the channel characteristics and it needs to be modified accordingly. This analysis is extended further with the study of frequency offset error and its correction. The unbiased Cramer Rao Lower Bound (CRLB) of estimation error is calculated and supported by computer simulation. The performance of an MB-OFDM system with frequency offset correction in terms of Bit-Error-Rate (BER) is also reported.

Transceiver Optimization for Multi-Antenna Device-to-Device Communications

It has been shown that the deployment of device-to-device(D2D) communication in cellular systems can provide better support for local services. However, improper design of the hybrid system may cause severe interference between cellular and D2D links. In this paper, we consider transceiver design for the system employing multiple antennas to mitigate the interference. The precoder and decoder matrices are optimized in terms of sum mean squared error(MSE) and capacity, respectively. For the MSE minimization problem, we present an alternative transceiver optimization algorithm. While for the non-convex capacity maximization problem, we decompose the primal problem into a sequence of standard convex quadratic programs for efficient optimization. The evaluation of our proposed algorithms for performance enhancement of the entire D2D integrated cellular system is carried out through simulations.

Design of an adaptive precoding/STBC baseband transceiver on a reconfigurable architecture

Precoding and space-time block coding （STBC）techniques using the uniform channel decomposition （UCD）are proposed to improve the bit error rate （BER） of themultiple-antenna communication system, but at a cost of areduced data rate. In order to achieve a higher overall systemperformance, a novel adaptive transceiver architecture whichflexibly combines both UCD and UCD ＋ STBC technologies isproposed. The channel state information （CSI） feedback pathwas added to the precoder to select which coding method wasto be used, i.e. UCD alone or UCD ＋ STBC. With thesmaller constellation sizes, Matlab simulation results showthat, the adaptive transceiver architecture will select the UCD-only mode under the higher SNR conditions in order to achievea higher bit rate. The UCD ＋ STBC mode will be selectedunder the lower SNR conditions （e. g., SNR 〈 10 dB） inorder to maintain good BER performance at the cost of areduced data rate. This architecture was implemented andverified using both UMC 0.18 ASIC process technology and aXilinx xc4vlx Virtex-4 FPGA at 150 MHz. The simulationresults demonstrate that the required number of reconfigurablearithmetic unit slices grows linearly with the channel matrixsize, while the number of adder array unit and reconfigurablelogic unit slices increases slightly with the constellation size.