In this paper, two kinds of fuzzy logic named “fuzzy intervalvalue logic” and “uzzy distributedvalue logic”with truth values in fuzzy intervals and probabilistic distribution functions are presented, respectively...In this paper, two kinds of fuzzy logic named “fuzzy intervalvalue logic” and “uzzy distributedvalue logic”with truth values in fuzzy intervals and probabilistic distribution functions are presented, respectively, and the syllogism (modus ponens) is given for each logic. It has been pointed out that they will have various applications in knowledgebased systems and other artificial intelligence fields.展开更多
Residue Number System (RNS) has proved shaping the Digital Signal Processing (DSP) units into highly parallel, faster and secured entities. The computational complexity of the multiplication process for a RNS based de...Residue Number System (RNS) has proved shaping the Digital Signal Processing (DSP) units into highly parallel, faster and secured entities. The computational complexity of the multiplication process for a RNS based design can be reduced by indulging Logarithmic Number System (LNS). The combination of these unusual number systems forms Residue Logarithmic Number System (RLNS) that provides simple internal architectures. Till date RLNS based processing units are designed for binary logic based circuits. In order to reduce the number of input output signals in a system, the concept of Multiple Valued Logic (MVL) is introduced in literature. In that course of research, this paper uses Tri Valued Logic (TVL) in RLNS technique proposed, to further reduce the chip area and delay value. Thus in this research work three different concepts are proposed, it includes the design of multiplier for RLNS based application for number of bits 8, 16 and 32. Next is the utilization of TVL in the proposed multiplication structure for RLNS based system along with the error correction circuits for the ternary logarithmic and antilogarithmic conversion process. Finally the comparison of the two multiplication schemes with the existing research of multiplier design for RNS based system using booth encoding concepts. It can be found that the proposed technique using TVL saves on an average of about 63% of area occupied and 97% of delay value respectively than the existing technique.展开更多
A new explanation of quaternary Q gate expression in Post algebra is given in this paper by using transmission function theory proposed in [1] and the quaternary ECL Q gate circuit is de- signed.The SPICE2 simulation ...A new explanation of quaternary Q gate expression in Post algebra is given in this paper by using transmission function theory proposed in [1] and the quaternary ECL Q gate circuit is de- signed.The SPICE2 simulation to this circuit has confirmed that it has desired logical function and is totally compatible with various quaternary ECL circuits proposed before.展开更多
文摘In this paper, two kinds of fuzzy logic named “fuzzy intervalvalue logic” and “uzzy distributedvalue logic”with truth values in fuzzy intervals and probabilistic distribution functions are presented, respectively, and the syllogism (modus ponens) is given for each logic. It has been pointed out that they will have various applications in knowledgebased systems and other artificial intelligence fields.
文摘Residue Number System (RNS) has proved shaping the Digital Signal Processing (DSP) units into highly parallel, faster and secured entities. The computational complexity of the multiplication process for a RNS based design can be reduced by indulging Logarithmic Number System (LNS). The combination of these unusual number systems forms Residue Logarithmic Number System (RLNS) that provides simple internal architectures. Till date RLNS based processing units are designed for binary logic based circuits. In order to reduce the number of input output signals in a system, the concept of Multiple Valued Logic (MVL) is introduced in literature. In that course of research, this paper uses Tri Valued Logic (TVL) in RLNS technique proposed, to further reduce the chip area and delay value. Thus in this research work three different concepts are proposed, it includes the design of multiplier for RLNS based application for number of bits 8, 16 and 32. Next is the utilization of TVL in the proposed multiplication structure for RLNS based system along with the error correction circuits for the ternary logarithmic and antilogarithmic conversion process. Finally the comparison of the two multiplication schemes with the existing research of multiplier design for RNS based system using booth encoding concepts. It can be found that the proposed technique using TVL saves on an average of about 63% of area occupied and 97% of delay value respectively than the existing technique.
基金The subject is supported by Zhejiang Provincial Natural Science Foundation.
文摘A new explanation of quaternary Q gate expression in Post algebra is given in this paper by using transmission function theory proposed in [1] and the quaternary ECL Q gate circuit is de- signed.The SPICE2 simulation to this circuit has confirmed that it has desired logical function and is totally compatible with various quaternary ECL circuits proposed before.
