Wigner-Ville distribution and cross Wigner-Ville distribution of noisy signals

The Wigner-Ville distribution （WVD） and the cross Wigner-Ville distribution （XWVD） have been shown to be efficient in the estimation of instantaneous frequency （IF）. But the statistical result of the IF estimation from XWVD peak is much better than using WVD peak. The reason is given from a statistical point of view. Theoretical studies show that XWVD of the analyzed signal can be estimated from XWVD of the noise-contaminated signal. The estimation is unbiased, and the variance is equal to that of noise. In this case, WVD cannot be estimated from W-VD of the noise-contaminated signal. Therefore, higher SNR is required when WVD is used to analyze signals.

Increase of brightness and transmission efficiency in fiat panel display through serial synchronous scanning mode with double buffers

This paper presents a serial synchronous scanning mode in fiat panel display （FPD） by adding a latch buffer between the serializer and the driving buffer. Comparing with conventional techniques, the proposed structure can efficiently reduce the brightness loss and improve the transmission performance. Theoretical analysis and experimental results show that the ratio between the lightest weight display time and the relative transmission time is a tradeoff between brightness loss and transmission efficiency.

Simulation realization of skip cycle mode integrated control circuit in the switching power supply with low standby loss

This paper explores and proposes a design solution of an integrated skip cycle mode （SCM） control circuit with a simple structure. The design is simulated and implemented with XD10H-1.0μm modular DIMOS 650 V process. In order to meet the requirement of a wide temperature range and high yields of products, the schematic extracted from the layout is simulated with five process corners at 27℃ and 90℃. Simulation results demonstrate that the proposed integrated circuit is immune to noise and achieves skipping cycle control when switching mode power supply （SMPS） works with low load or without load.

Fast Iterative Closest Point-Simultaneous Localization and Mapping(ICP-SLAM)with Rough Alignment and Narrowing-Scale Nearby Searching

Two deficiencies in traditional iterative closest pointsimultaneous localization and mapping( ICP-SLAM) usually result in poor real-time performance. On one hand, relative position between current scan frame and global map cannot be previously known. As a result, ICP algorithm will take much amount of iterations to reach convergence. On the other hand,establishment of correspondence is done by global searching, which requires enormous computational time. To overcome the two problems,a fast ICP-SLAM with rough alignment and narrowing-scale nearby searching is proposed. As for the decrease of iterative times,rough alignment based on initial pose matrix is proposed. In detail,initial pose matrix is obtained by micro-electro-mechanical system( MEMS) magnetometer and global landmarks. Then rough alignment will be applied between current scan frame and global map at the beginning of ICP algorithm with initial pose matrix. As for accelerating the establishment of correspondence, narrowingscale nearby searching with dynamic threshold is proposed,where match-points are found within a progressively constrictive range.Compared to traditional ICP-SLAM,the experimental results show that the amount of iteration for ICP algorithm to reach convergence reduces to 92. 34% and ICP algorithm runtime reduces to 98. 86% on average. In addition,computational cost is kept in a stable level due to the eliminating of the accumulation of computational consumption. Moreover,great improvement can also been achieved in SLAM quality and robustness.

Area-time associated test cost model for SoC and lower bound of test time

A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip （SoC） test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.

Analyzing and Seeking Minimum Test Instruction Set of Digital Signal Processor for Motor Control

The relativity of instructions of motor control digital signal processor (MCDSP) in the design is analyzed. A method for obtaining a minimum instruction set in plac e of the complete instruction set during generation of testing procedures is giv en in terms of the processor presentation matrix between micro-operators and in structions of MCDSP.

Searching high gray scale FPD scanning matrix based on PSO

With the increase of gray scale and flat panel display （FPD） size, subspace bitwise scanning strategy can be replaced traditional scanning method to cut down frame frequency. However, the direct searching strategy （DSS） becomes unfeasible to obtain corresponding high gray scale scanning matrix. Thus, particle swarm optimization （PSO） is introduced to accelerate searching for high gray scale weights scanning matrix （WSM） with its parallelism and global optimization feature. Finally a WSM of 256 gray scales is found out successfully with Matlab, which both gray linearity and scanning efficiency are satisfied.

A High-Speed Dual Modulus Prescaler Using 0.25 μm CMOS Technology

A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5 V, 0.25 μm CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at 2.5 V, the circuit consumes only 4.6 mA at an input frequency 2.5 GHz.

Scheduling method based on virtual flattened architecture for Hierarchical system-on-chip

As the technology of IP-core-reused has been widely used, a lot of intellectual property （IP） cores have been embedded in different layers of system-on-chip （SOC）. Although the cycles of development and overhead are reduced by this method, it is a challenge to the SOC test. This paper proposes a scheduling method based on the virtual flattened architecture for hierarchical SOC, which breaks the hierarchical architecture to the virtual flattened one. Moreover, this method has more advantages compared with the traditional one, which tests the parent cores and child cores separately. Finally, the method is verified by the ITC＇02 benchmark, and gives good results that reduce the test time and overhead effectively.

Non-Intrusive Design of Self-Checking FSM Based on Convolutional Codes

A non-intrusive design of self-checking finite state machines (FSMs) in VLSI circuits was investigated using convolutional codes. We propose a novel scheme which cannot only detect but also correct errors occurred in FSM states. The error state will be corrected and sent back to the FSM, so that the concurrent error in the current state is detected and corrected immediately. Moreover, we realize the IP core of the self-checking module by SMIC 0.25-μm CMOS technology and also simulate its function in FPGA.