A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18μm CMOS process is introduced.By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing...A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18μm CMOS process is introduced.By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time,the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased,compared with traditional prescalers.Measurement results show that this synthesizer achieves an in-band phase noise of-87 dBc/Hz at 15 kHz offset,with spurs less than-65 dBc.The whole synthesizer consumes 6 mA in the case of a 1.8 V supply,and its core area is 0.6 mm^2.展开更多
The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented.The large tuning range is achieved by tuning curve compensation usin...The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented.The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank,which reduces the power consumption and obtains better phase noise performance. The circuit is validated by simulations and fabricated in a standard 0.18μm 1P6M CMOS process.Close-loop phase noise measured is lower than-95 dBc at 200 kHz offset while the measured tuning range is 21.5%from 1.47 to 1.83 GHz.The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply. The whole silicon required is only 0.53 mm^2.展开更多
基金Project supported by the National Municipal Sci-Tech Project of China(No.2009ZX01031-002-008)the National High Technology Research and Development Program of China(No.2007AA12Z344).
文摘A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18μm CMOS process is introduced.By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time,the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased,compared with traditional prescalers.Measurement results show that this synthesizer achieves an in-band phase noise of-87 dBc/Hz at 15 kHz offset,with spurs less than-65 dBc.The whole synthesizer consumes 6 mA in the case of a 1.8 V supply,and its core area is 0.6 mm^2.
基金supported by the National High Technology Research and Development Program of China(No.2007AA12Z344).
文摘The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented.The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank,which reduces the power consumption and obtains better phase noise performance. The circuit is validated by simulations and fabricated in a standard 0.18μm 1P6M CMOS process.Close-loop phase noise measured is lower than-95 dBc at 200 kHz offset while the measured tuning range is 21.5%from 1.47 to 1.83 GHz.The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply. The whole silicon required is only 0.53 mm^2.
