This paper presents a 400-MS/s 12-bit CMOS current-steering digital-to-analog converter （DAC）. The proposed DAC adapts 6＋2＋4 segmented architecture and a modified switching scheme to improve dynamic and static per...This paper presents a 400-MS/s 12-bit CMOS current-steering digital-to-analog converter （DAC）. The proposed DAC adapts 6＋2＋4 segmented architecture and a modified switching scheme to improve dynamic and static performance. The measured spurious-free dynamic range is up to 77.18 dB at 400 MS/s with a 10 MHz input signal. The full-scale output current is 20 mA with a 1.8 V single power supply. The core area occupies 0.6 mm2 in a standard 1P-6M 0.18-μm CMOS process.展开更多
文摘This paper presents a 400-MS/s 12-bit CMOS current-steering digital-to-analog converter （DAC）. The proposed DAC adapts 6＋2＋4 segmented architecture and a modified switching scheme to improve dynamic and static performance. The measured spurious-free dynamic range is up to 77.18 dB at 400 MS/s with a 10 MHz input signal. The full-scale output current is 20 mA with a 1.8 V single power supply. The core area occupies 0.6 mm2 in a standard 1P-6M 0.18-μm CMOS process.
