This paper presents a 10-bit 50-MS/s subrange successive-approximation register （SAR） analog-to- digital converter （ADC） composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi- compa...This paper presents a 10-bit 50-MS/s subrange successive-approximation register （SAR） analog-to- digital converter （ADC） composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi- comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1PSM 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio （SNDR） and consumes 186μW at 50 MS/s with a 1-V supply, resulting in a figure of merit （FOM） of 12 fJ/conversion-step. The core area is only 0.045 mm2.展开更多
基金Project supported by the National Natural Science Foundation of China(Nos.61204033,61331015)the Fundamental Research Funds for the Central Universities(No.WK2100230015)the Funds of Science and Technology on Analog Integrated Circuit Laboratory(No.9140C090111150C09041)
文摘This paper presents a 10-bit 50-MS/s subrange successive-approximation register （SAR） analog-to- digital converter （ADC） composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi- comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1PSM 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio （SNDR） and consumes 186μW at 50 MS/s with a 1-V supply, resulting in a figure of merit （FOM） of 12 fJ/conversion-step. The core area is only 0.045 mm2.
