A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant ac...A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator（VCO）are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature（IQ）signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency（RF） complementary metal oxide semiconductor transistor （CMOS）technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.展开更多
A Gm-C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 μm CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filte...A Gm-C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 μm CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage.展开更多
A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge...A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.展开更多
基金The National High Technology Research and Development Program of China (863 Program)(No.2007AA01Z2A7)the Scienceand Technology Program of Zhejiang Province (No.2008C16017)
文摘A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator（VCO）are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature（IQ）signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency（RF） complementary metal oxide semiconductor transistor （CMOS）technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.
基金Project supported by the National High Technology Research and Development Program of China(No.2007AA01Z2A7)the 5th Program of Six Talent Summits of Jiangsu Province,China.
文摘A Gm-C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 μm CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage.
基金Project supported by the National High Technology Research and Development Program of China(No.2007AA01Z2A7)
文摘A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.
