A 3-5 GHz broadband flat gain differential low noise amplifier(LNA) is designed for the impulse radio ultra-wideband(IR-UWB) system.The gain-flatten technique is adopted in this UWB LNA.Serial and shunt peaking techni...A 3-5 GHz broadband flat gain differential low noise amplifier(LNA) is designed for the impulse radio ultra-wideband(IR-UWB) system.The gain-flatten technique is adopted in this UWB LNA.Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product(GBW).Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations.The prototype is fabricated in the SMIC 0.18μm RF CMOS process.Measurement results show a 3-dB gain bandwidth of 2.4-5.5 GHz with a maximum power gain of 13.2 dB.The excellent gain flatness is achieved with±0.45 dB gain fluctuations across 3-5 GHz and the minimum noise figure(NF) is 3.2 dB over 2.5-5 GHz.This circuit also shows an excellent input matching characteristic with the measured S_(11) below-13 dB over 2.9-5.4 GHz.The input-referred 1-dB compression point(IP1dB) is-11.7 dBm at 5 GHz.The differential circuit consumes 9.6 mA current from a supply of 1.8 V.展开更多
A differential power amplifier(PA),designed using the linear-phase filter model,for a BPSK modulated ultra-wideband(UWB) system operating in the 3-5 GHz frequency range is presented.The proposed PA was fabricated usin...A differential power amplifier(PA),designed using the linear-phase filter model,for a BPSK modulated ultra-wideband(UWB) system operating in the 3-5 GHz frequency range is presented.The proposed PA was fabricated using 0.18μm SMIC CMOS technology.To achieve sufficient linearity and efficiency,this PA operates in the class-AB region,delivering an output power of 8.5 dBm at an input-1 dB compression point of -0.5 dBm.It consumes 28.8 mW, realizing a flat gain of 9.11±0.39 dB and a very low group delay ripple of±8 ps across the whole band of operation.展开更多
This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process,the operating range of the synthesizer is 3.74 to 4....This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process,the operating range of the synthesizer is 3.74 to 4.44 GHz.By using an 18-bit third-orderΣ-Δmodulator,the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz.The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8°respectively.The measured phase noise is-116 dBc/Hz at 3 MHz offset for a 4 GHz output. Measured spurious tones are lower than-60 dBc.The settling time is within 80μs.The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.展开更多
基金supported by the State Hi-Tech Research and Development Program(No.2007AA01Z2b2)
文摘A 3-5 GHz broadband flat gain differential low noise amplifier(LNA) is designed for the impulse radio ultra-wideband(IR-UWB) system.The gain-flatten technique is adopted in this UWB LNA.Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product(GBW).Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations.The prototype is fabricated in the SMIC 0.18μm RF CMOS process.Measurement results show a 3-dB gain bandwidth of 2.4-5.5 GHz with a maximum power gain of 13.2 dB.The excellent gain flatness is achieved with±0.45 dB gain fluctuations across 3-5 GHz and the minimum noise figure(NF) is 3.2 dB over 2.5-5 GHz.This circuit also shows an excellent input matching characteristic with the measured S_(11) below-13 dB over 2.9-5.4 GHz.The input-referred 1-dB compression point(IP1dB) is-11.7 dBm at 5 GHz.The differential circuit consumes 9.6 mA current from a supply of 1.8 V.
基金supported by the National High Technology Research and Development Program of China(No.2007AA01Z2b2).
文摘A differential power amplifier(PA),designed using the linear-phase filter model,for a BPSK modulated ultra-wideband(UWB) system operating in the 3-5 GHz frequency range is presented.The proposed PA was fabricated using 0.18μm SMIC CMOS technology.To achieve sufficient linearity and efficiency,this PA operates in the class-AB region,delivering an output power of 8.5 dBm at an input-1 dB compression point of -0.5 dBm.It consumes 28.8 mW, realizing a flat gain of 9.11±0.39 dB and a very low group delay ripple of±8 ps across the whole band of operation.
基金supported by the National High Technology Research and Development Program of China(No.2007AA01Z2b2).
文摘This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process,the operating range of the synthesizer is 3.74 to 4.44 GHz.By using an 18-bit third-orderΣ-Δmodulator,the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz.The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8°respectively.The measured phase noise is-116 dBc/Hz at 3 MHz offset for a 4 GHz output. Measured spurious tones are lower than-60 dBc.The settling time is within 80μs.The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.
