To meet the requirements of the low power Zigbee system, VCO design optimizations of phase noise, power consumption and frequency tuning are discussed in this paper. Both flicker noise of tail bias transistors and up-...To meet the requirements of the low power Zigbee system, VCO design optimizations of phase noise, power consumption and frequency tuning are discussed in this paper. Both flicker noise of tail bias transistors and up-conversion of flicker noise from cross-coupled pair are reduced by improved self-switched biasing technology, leading to low close-in phase noise. Low power is achieved by low supply voltage and triode region biasing. To linearly tune the frequency and get constant gain, distributed varactor structure is adopted. The proposed VCO is fabricated in SMIC 0.18-#m CMOS process. The measured linear tuning range is from 2.38 to 2.61 GHz. The oscillator exhibits low phase noise of-77.5 dBc/Hz and -122.8 dBc/Hz at l0 kHz and 1 MHz offset, respectively, at 2.55 GHz oscillation frequency while dissipating 2.7 mA from 1.2 V supply voltage, which well meet design specifications.展开更多
A low-power, high-FoM （figure of merit）, time-domain VCO （voltage controlled oscillator）-based ADC （analog-to-digital converter） in 65 nm CMOS technology is proposed. An asynchronous sigma-delta modulator （ASDM...A low-power, high-FoM （figure of merit）, time-domain VCO （voltage controlled oscillator）-based ADC （analog-to-digital converter） in 65 nm CMOS technology is proposed. An asynchronous sigma-delta modulator （ASDM） is used to convert the voltage input signal to a square wave time signal, where the information is contained in its pulse-width. A time-domain quantizer, which uses VCO to convert voltage to frequency, is adopted, while the XOR （exclusive-OR） gate circuits convert the frequency information to digital representatives. The ASDM does not need an external clock, so there is no quantization noise. At the same time, the ASDM applies a harmonic- distortion-cancellation technique to its transconductance stage, which increases the SNDR （signal to noise and distortion ratio） performance of the ASDM. Since the output of the ASDM is a two-level voltage signal, the VCO＇s V-F （voltage to frequency） conversion curve is always linear. The XOR phase quantizer has an inherent feature of first-order noise-shaping. It puts the ADC＇s low-frequency output noise to high-frequency which is further filtered out by a low-pass filter. The proposed ADC achieves an SNR/SNDR of 54. dB/54.3 dB in the 8 MHz bandwidth, while consuming 2.8 mW. The FoM of the proposed ADC is a 334 fJ/conv-step.展开更多
基金supported by the National Science and Technology Major Project,China(No.2009ZX03006 009)the USTC and IMECAS Jointed Lab Micro-/Nano-Electronic System Integration R&D Center(MESIC)
文摘To meet the requirements of the low power Zigbee system, VCO design optimizations of phase noise, power consumption and frequency tuning are discussed in this paper. Both flicker noise of tail bias transistors and up-conversion of flicker noise from cross-coupled pair are reduced by improved self-switched biasing technology, leading to low close-in phase noise. Low power is achieved by low supply voltage and triode region biasing. To linearly tune the frequency and get constant gain, distributed varactor structure is adopted. The proposed VCO is fabricated in SMIC 0.18-#m CMOS process. The measured linear tuning range is from 2.38 to 2.61 GHz. The oscillator exhibits low phase noise of-77.5 dBc/Hz and -122.8 dBc/Hz at l0 kHz and 1 MHz offset, respectively, at 2.55 GHz oscillation frequency while dissipating 2.7 mA from 1.2 V supply voltage, which well meet design specifications.
文摘A low-power, high-FoM （figure of merit）, time-domain VCO （voltage controlled oscillator）-based ADC （analog-to-digital converter） in 65 nm CMOS technology is proposed. An asynchronous sigma-delta modulator （ASDM） is used to convert the voltage input signal to a square wave time signal, where the information is contained in its pulse-width. A time-domain quantizer, which uses VCO to convert voltage to frequency, is adopted, while the XOR （exclusive-OR） gate circuits convert the frequency information to digital representatives. The ASDM does not need an external clock, so there is no quantization noise. At the same time, the ASDM applies a harmonic- distortion-cancellation technique to its transconductance stage, which increases the SNDR （signal to noise and distortion ratio） performance of the ASDM. Since the output of the ASDM is a two-level voltage signal, the VCO＇s V-F （voltage to frequency） conversion curve is always linear. The XOR phase quantizer has an inherent feature of first-order noise-shaping. It puts the ADC＇s low-frequency output noise to high-frequency which is further filtered out by a low-pass filter. The proposed ADC achieves an SNR/SNDR of 54. dB/54.3 dB in the 8 MHz bandwidth, while consuming 2.8 mW. The FoM of the proposed ADC is a 334 fJ/conv-step.
