A clock generator for a high-speed high-resolution pipelined A/D converter

A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented. The circuit is realized by a delay locked loop （DLL）, and a new differential structure is used to improve the precision of the charge pump. Meanwhile, a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition. The proposed circuit, designed by SMIC 0.18 um 3.3 V CMOS technology, is used as a clock generator for a 14 bit 100 MS/s pipelined ADC. The simulation results have shown that the duty cycle ranged from 10% to 90% and can be adjusted. The average duty cycle error is less than 1%. The lock-time is only 13 clock cycles. The active area is 0.05 mm2 and power consumption is less than 15 mW.

A programmable MDAC with power scalability

A programmable high precision multiplying DAC （MDAC） is proposed. The MDAC incorporates a frequency-current converter （FCC） to adjust the power versus sampling rate and a programmable operational am- plifier （POTA） to achieve the tradeoff between resolution and power of the MDAC, which makes the MDAC suitable for a 12 bit SHA-less pipelined ADC. The prototype of the proposed pipelined ADC is implemented in an SMIC CMOS 0.18 μm 1P6M process. Experimental results demonstrate that power of the proposed ADC varies from 15.4 mW （10 MHz） to 63 mW （100 MHz） while maintaining an SNDR of 60.5 to 63 dB at all sampling rates. The differential nonlinearity and integral nonlinearity without any calibration are no more than 2.2/-1 LSB and 1.6/-1.9 LSB, respectively.

SHA-less architecture with enhanced accuracy for pipelined ADC

A new design technique for merging the front-end sample-and-hold amplifier（SHA） into the first multiplying digital-to-analog converter（MDAC） is presented.For reducing the aperture error in the first stage of the pipelined ADC,a symmetrical structure is used in a flash ADC and MDAC.Furthermore,a variable resistor tuning network is placed at the flash input to compensate for different cutoff frequencies of the input impedances of the flash and MDAC.The circuit also has a clear clock phase in the MDAC and separate sampling capacitors in the flash ADC to eliminate the nonlinear charge kickback to the input signal.The proposed circuit,designed using ASMC 0.35-μm BiCMOS technology,occupies an area of 1.4 x 9 mm^2 and is used as the front-end stage in a 14-bit 125-MS/s pipelined ADC.After the trim circuit is enabled,the measured signal-to-noise ratio is improved from 71.5 to 73.6 dB and the spurious free dynamic range is improved from 80.5 to 83.1 dB with a 30.8 MHz input. The maximum input frequency is up to 150 MHz without steep performance degradations.