基于混合波束赋形架构的数字中频系统方案设计

对基于混合波束赋形的系统架构进行了研究。提出了新型的混合波束赋形架构,并采用高集成宽带收发芯片AD9361与全可编程片上系统进行多通道数字中频系统的搭建。测试结果表明该方案稳定可靠,满足大带宽高速传输的需求。

基于0.13 μm SiGe BiCMOS工艺的Ka波段低噪声放大器的设计

介绍了一款基于SiGe BiCMOS工艺的Ka波段低噪声放大器(LNA)的设计与测试。分析了毫米波频段硅基集成电路的匹配设计方法,给出了HBT晶体管电流密度与噪声系数的关系,以及最佳噪声偏置点的选取方法。并基于以上方法设计了单级共基共射低噪声放大器,LNA芯片基于Global Foundry 8HP工艺流片验证。测试结果表明,该LNA实现了30~40GHz的-1dB带宽、小于3.5dB的噪声系数以及6.2dBm的1dB压缩输出功率(P-1dB);输入输出反射系数均小于-15dB,中心频率(35GHz)处增益为7.2dB(单级),LNA的直流电流为6.7mA,电源电压为1.8V。

软件化雷达技术发展趋势与挑战

本报告论述了软件化雷达(Software Defined Radar,SDR)的内涵、基本特点和总体架构,并分析了软件化雷达的中移相器和变频器的数字化的发展趋势,论述了SDR对ADC动态范围、量化精度以及采样速度的要求,分析了低成本有源相控阵雷达架构在未来SDR架构中的应用前景。

高速磁悬浮列车通信天线罩流固耦合数值模拟

为了获得高速工况下车载天线罩的气动特性和罩体结构强度,建立了天线罩外流场仿真模型,得到了天线罩外流场的气动特性。进一步提取天线罩外表面气动压力,进行天线罩结构强度分析。流固耦合仿真结果表明,天线罩最大等效应力远小于罩体材料的屈服强度。计算结果可作为天线罩气动外形和结构强度设计的参考依据。

A wideband current-commutating passive mixer for multi-standard receivers in a 0.18μm CMOS

This paper reports a wideband passive mixer for direct conversion multi-standard receivers.A brief comparison between current-commutating passive mixers and active mixers is presented.The effect of source and load impedance on the linearity of a mixer is analyzed.Specially,the impact of the input impedance of the transimpedance amplifier（TIA）,which acts as the load impedance of a mixer,is investigated in detail.The analysis is verified by a passive mixer implemented with 0.18 μm CMOS technology.The circuit is inductorless and can operate over a broad frequency range.On wafer measurements show that,with radio frequency（RF） ranges from 700 MHz to 2.3 GHz,the mixer achieves 21 dB of conversion voltage gain with a-1 dB intermediate frequency（IF） bandwidth of 10 MHz.The measured IIP3 is 9 dBm and the measured double-sideband noise figure（NF） is 10.6 dB at 10 MHz output.The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.

A wideband LNA employing gate-inductive-peaking and noise-canceling techniques in 0.18μm CMOS

This paper presents a wideband low noise amplifier （LNA） for multi-standard radio applications. The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gate- inductive-peaking technique. High-frequency noise performance is consequently improved by the flattened gain over the entire operating frequency band. Fabricated in 0.18 μm CMOS process, the LNA achieves 2.5 GHz of -3 dB bandwidth and 16 dB of gain. The gain variation is within 4-0.8 dB from 300 MHz to 2.2 GHz. The measured noise figure （NF） and average IIP3 are 3.4 dB and -2 dBm, respectively. The proposed LNA occupies 0.39 mm2 core chip area. Operating at 1.8 V, the LNA drains a current of 11.7 mA.

A reconfigurable passive mixer for multimode multistandard receivers in 0.18 μm CMOS

This paper presents a reconfigurable quadrature passive mixer for multimode multistandard receivers. By using controllable transconductor and transimpedance-amplifier stages, the voltage conversion gain of the mixer is reconfigured according to the requirement of the selected communication standard Other characteristics such as noises figure, linearity and power consumption are also reconfigured consequently. The design concept is verified by implementing a quadrature passive mixer in 0.18 μm CMOS technology. On wafer measurement results show that, with the input radio frequency ranges from 700 MHz to 2.3 GHz, the mixer achieves a controllable voltage conversion gain from 4 to 22 dB with a step size of 6 dB. The measured maximum IIP3 is 8.5 dBm and the minimum noise figure is 8.0 dB. The consumed current for a single branch （I or Q） ranges from 3.1 to 5.6 mA from a 1.8 V supply voltage. The chip occupies an area of 0.71 mm2 including pads.