在无电池胎压监测系统中,为降低ADC功耗,采用了一种改进的DAC结构并设计实现了一款低功耗8bit SAR ADC.与传统结构中采用Vref作为参考电压相比,设计中DAC采用Vref/2作为参考电压,并实现了（0,Vref）的满量程输入,在DAC的量化中可降低87...在无电池胎压监测系统中,为降低ADC功耗,采用了一种改进的DAC结构并设计实现了一款低功耗8bit SAR ADC.与传统结构中采用Vref作为参考电压相比,设计中DAC采用Vref/2作为参考电压,并实现了（0,Vref）的满量程输入,在DAC的量化中可降低87.5%动态功耗.在完成电路和版图设计后,仿真结果显示,在采样率为2kS/s,电源电压为3V,参考电压为1.5V时,ADC平均动态功耗为0.9μW.MATLAB频谱分析显示,ADC有效位数为7.6bit,无杂散动态范围为63.2dB,工作温度范围为-40~125℃.并已运用于胎压监测SoC中提交0.35μm BCD汽车电子工艺流片.展开更多
Modular inversion is one of the key arithmetic operations in public key cryptosystems, so low-cost, high-speed hardware implementation is absolutely necessary. This paper presents an algorithm for prime fields for har...Modular inversion is one of the key arithmetic operations in public key cryptosystems, so low-cost, high-speed hardware implementation is absolutely necessary. This paper presents an algorithm for prime fields for hardware implementation. The algorithm involves only ordinary addition/subtraction and does not need any modular operations, multiplications or divisions. All of the arithmetic operations in the algorithm can be accomplished by only one adder, so it is very suitable for fast very large scale integration (VLSI) implementation. The VLSI implementation of the algorithm is also given with good performance and low silicon penalty.展开更多
文摘在无电池胎压监测系统中,为降低ADC功耗,采用了一种改进的DAC结构并设计实现了一款低功耗8bit SAR ADC.与传统结构中采用Vref作为参考电压相比,设计中DAC采用Vref/2作为参考电压,并实现了（0,Vref）的满量程输入,在DAC的量化中可降低87.5%动态功耗.在完成电路和版图设计后,仿真结果显示,在采样率为2kS/s,电源电压为3V,参考电压为1.5V时,ADC平均动态功耗为0.9μW.MATLAB频谱分析显示,ADC有效位数为7.6bit,无杂散动态范围为63.2dB,工作温度范围为-40~125℃.并已运用于胎压监测SoC中提交0.35μm BCD汽车电子工艺流片.
基金Supported by the Prom otion Plan of the Ministry of E-ducation and the National Natural Science Foundationof China(No.2 0 0 2 AA14 10 4 0 )
文摘Modular inversion is one of the key arithmetic operations in public key cryptosystems, so low-cost, high-speed hardware implementation is absolutely necessary. This paper presents an algorithm for prime fields for hardware implementation. The algorithm involves only ordinary addition/subtraction and does not need any modular operations, multiplications or divisions. All of the arithmetic operations in the algorithm can be accomplished by only one adder, so it is very suitable for fast very large scale integration (VLSI) implementation. The VLSI implementation of the algorithm is also given with good performance and low silicon penalty.
