通过二维器件仿真,分析单指、多指18V nLDMOS器件在静电放电防护中电流分布的非均匀性问题。经仿真分析可知,寄生三极管的部分导通是单指器件电流分布不均匀的原因;器件的大面积特征、材料本身的不均匀性等因素导致叉指不同时触发,同时...通过二维器件仿真,分析单指、多指18V nLDMOS器件在静电放电防护中电流分布的非均匀性问题。经仿真分析可知,寄生三极管的部分导通是单指器件电流分布不均匀的原因;器件的大面积特征、材料本身的不均匀性等因素导致叉指不同时触发,同时,由于nLDMOS各叉指基极被深N阱隔离,先被触发的叉指无法抬高未触发叉指的基极电位帮助其开启,是多指器件电流分布不均匀的原因。器件的TLP(Transmission line pulse)测试结果与仿真分析吻合,指长分别为50μm和90μm的单指器件ESD电流泄放能力分别为21mA/μm和15mA/μm;指长为50μm的单指、双指、四指和八指器件的ESD失效电流分别为1.037A、1.055A、1.937A和1.710A,不与指数成比例增大。展开更多
A novel LDNMOS embedded silicon controlled rectifier(SCR) was proposed to enhance ESD robustness of high-voltage(HV) LDNMOS based on a 0.5 μm 18 V CDMOS process. A two-dimensional(2D) device simulation and a transmis...A novel LDNMOS embedded silicon controlled rectifier(SCR) was proposed to enhance ESD robustness of high-voltage(HV) LDNMOS based on a 0.5 μm 18 V CDMOS process. A two-dimensional(2D) device simulation and a transmission line pulse(TLP) testing were used to analyze the working mechanism and ESD performance of the novel device. Compared with the traditional GG-LDNMOS, the secondary breakdown current(It2) of the proposed device can successfully increase from 1.146 A to 3.169 A with a total width of 50 μm, and ESD current discharge efficiency is improved from 0.459 m A/μm2 to 1.884 m A/μm2. Moreover, due to their different turn-on resistances(Ron), the device with smaller channel length(L) owns a stronger ESD robustness per unit area.展开更多
文摘通过二维器件仿真,分析单指、多指18V nLDMOS器件在静电放电防护中电流分布的非均匀性问题。经仿真分析可知,寄生三极管的部分导通是单指器件电流分布不均匀的原因;器件的大面积特征、材料本身的不均匀性等因素导致叉指不同时触发,同时,由于nLDMOS各叉指基极被深N阱隔离,先被触发的叉指无法抬高未触发叉指的基极电位帮助其开启,是多指器件电流分布不均匀的原因。器件的TLP(Transmission line pulse)测试结果与仿真分析吻合,指长分别为50μm和90μm的单指器件ESD电流泄放能力分别为21mA/μm和15mA/μm;指长为50μm的单指、双指、四指和八指器件的ESD失效电流分别为1.037A、1.055A、1.937A和1.710A,不与指数成比例增大。
基金Project(NCET-11-0975)supported by Program for New Century Excellent Talents in University of Ministry of Education of ChinaProjects(61233010,61274043)supported by the National Natural Science Foundation of China
文摘A novel LDNMOS embedded silicon controlled rectifier(SCR) was proposed to enhance ESD robustness of high-voltage(HV) LDNMOS based on a 0.5 μm 18 V CDMOS process. A two-dimensional(2D) device simulation and a transmission line pulse(TLP) testing were used to analyze the working mechanism and ESD performance of the novel device. Compared with the traditional GG-LDNMOS, the secondary breakdown current(It2) of the proposed device can successfully increase from 1.146 A to 3.169 A with a total width of 50 μm, and ESD current discharge efficiency is improved from 0.459 m A/μm2 to 1.884 m A/μm2. Moreover, due to their different turn-on resistances(Ron), the device with smaller channel length(L) owns a stronger ESD robustness per unit area.
