A 1,4-V 8-bit 300-MS/s folding and interpolating analog-to-digital converter（ADC） is proposed.Fabricated in the 0.13-μm CMOS process and occupying only 0.6-mm^2 active area,the ADC is especially suitable for embedd...A 1,4-V 8-bit 300-MS/s folding and interpolating analog-to-digital converter（ADC） is proposed.Fabricated in the 0.13-μm CMOS process and occupying only 0.6-mm^2 active area,the ADC is especially suitable for embedded applications.The system is optimized for a low-power purpose.Pipelining sampling switches help to cut down the extra power needed for complete settling.An averaging resistor array is placed between two folding stages for power-saving considerations.The converter achieves 43.4-dB signal-to-noise and distortion ratio and 53.3-dB spurious-free dynamic range at 1-MHz input and 42.1-dB and 49.5-dB for Nyquist input.Measured results show a power dissipation of 34 mW and a figure of merit of 1.14 pJ/convstep at 250-MHz sampling rate at 1.4-V supply.展开更多
基金Project supported by the National Science & Technology Major Projects,China(No.2009ZX03007-002-02)the Program of Shanghai Subject Chief Scientist Fund,China(No.08XD14007).
文摘A 1,4-V 8-bit 300-MS/s folding and interpolating analog-to-digital converter（ADC） is proposed.Fabricated in the 0.13-μm CMOS process and occupying only 0.6-mm^2 active area,the ADC is especially suitable for embedded applications.The system is optimized for a low-power purpose.Pipelining sampling switches help to cut down the extra power needed for complete settling.An averaging resistor array is placed between two folding stages for power-saving considerations.The converter achieves 43.4-dB signal-to-noise and distortion ratio and 53.3-dB spurious-free dynamic range at 1-MHz input and 42.1-dB and 49.5-dB for Nyquist input.Measured results show a power dissipation of 34 mW and a figure of merit of 1.14 pJ/convstep at 250-MHz sampling rate at 1.4-V supply.
