A fully integrated low-jitter, precise frequency CMOS phase-locked loop （PLL） clock for the phase change memory （PCM） drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detect...A fully integrated low-jitter, precise frequency CMOS phase-locked loop （PLL） clock for the phase change memory （PCM） drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector （PFD） with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator （VCO）, a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 #m CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM＇s program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.展开更多
A low ripple switched capacitor charge pump applicable to phase change memory （PCM） is presented. For high power efficiency, the selected charge pump topology can automatically change the power conversion ratio betw...A low ripple switched capacitor charge pump applicable to phase change memory （PCM） is presented. For high power efficiency, the selected charge pump topology can automatically change the power conversion ratio between 2X/1.5X modes with the input voltage. For a low output ripple, a novel operation mode is used. Compared with the conventional switched capacitor charge pump, the flying capacitor of the proposed charge pump is charged to Vo- 14n during the charge phase （Vo is the prospective output voltage）. In the discharge phase, the flying capacitor is placed in series with the Vin to transfer energy to the output, so the output voltage is regulated at Vo. A simulation was implemented for a DC input range of 1.6-2.1 V in on SMIC standard 40 nm CMOS process, the result shows that the new operation mode could regulate the output of about 2.5 V with a load condition from 0 to 10 mA, and the ripple voltage is lower than 4 mV. The maximum power efficiency reaches 91%.展开更多
基金Project supported by the National Key Basic Research Program of China(Nos.2010CB934300,2011CBA00607,2011CB9328004)the National Integrate Circuit Research Program of China(No.2009ZX02023-003)+2 种基金the National Natural Science Foundation of China(Nos.60906004,60906003,61006087,61076121,61176122,61106001)the Science and Technology Council of Shanghai(No. 11DZ2261000,1052nm07000,11QA 1407800)the Chinese Academy of Sciences(No.20110490761)
文摘A fully integrated low-jitter, precise frequency CMOS phase-locked loop （PLL） clock for the phase change memory （PCM） drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector （PFD） with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator （VCO）, a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 #m CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM＇s program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.
基金supported by the National Key Basic Research Program of China(Nos.2010CB934300,2011CBA00607,2011CB932800)the National Integrated Circuit Research Program of China(No.2009ZX02023-003)+1 种基金the National Natural Science Foundation of China(Nos. 60906004,60906003,61006087,61076121)the Science and Technology Council of Shanghai(No.1052nm07000)
文摘A low ripple switched capacitor charge pump applicable to phase change memory （PCM） is presented. For high power efficiency, the selected charge pump topology can automatically change the power conversion ratio between 2X/1.5X modes with the input voltage. For a low output ripple, a novel operation mode is used. Compared with the conventional switched capacitor charge pump, the flying capacitor of the proposed charge pump is charged to Vo- 14n during the charge phase （Vo is the prospective output voltage）. In the discharge phase, the flying capacitor is placed in series with the Vin to transfer energy to the output, so the output voltage is regulated at Vo. A simulation was implemented for a DC input range of 1.6-2.1 V in on SMIC standard 40 nm CMOS process, the result shows that the new operation mode could regulate the output of about 2.5 V with a load condition from 0 to 10 mA, and the ripple voltage is lower than 4 mV. The maximum power efficiency reaches 91%.
