为提高无人机避障的灵活性和可靠性,提出了一种基于LGMD(Lobula Giant Movement Detector)的无人机避障方法,通过将视场分割为上、下、左、右4个方位,形成4个方位竞争的LGMD(C-LGMD),并利用Matlab软件进行算法实现和视频仿真分析,最后...为提高无人机避障的灵活性和可靠性,提出了一种基于LGMD(Lobula Giant Movement Detector)的无人机避障方法,通过将视场分割为上、下、左、右4个方位,形成4个方位竞争的LGMD(C-LGMD),并利用Matlab软件进行算法实现和视频仿真分析,最后将算法移植到无人机硬件系统,开展悬停测试和实时飞行实验研究。由视频仿真分析和悬停测试结果表明,该算法能有效分辨来自不同方位的障碍物,具有较好的避障性能和鲁棒性;在实时飞行测试中,无人机在室内环境中可实现三维空间有效避障,验证了该算法的可靠性。研究结果为进一步探索无人机高效、可靠避障提供参考依据。展开更多
An IF-sampling S/H is presented,which adopts a flip-around structure,bottom-plate sampling technique and improved input bootstrapped switches.To achieve high sampling linearity over a wide input frequency range,the fl...An IF-sampling S/H is presented,which adopts a flip-around structure,bottom-plate sampling technique and improved input bootstrapped switches.To achieve high sampling linearity over a wide input frequency range,the floating well technique is utilized to optimize the input switches.Besides,techniques of transistor load linearization and layout improvement are proposed to further reduce and linearize the parasitic capacitance.The S/H circuit has been fabricated in 0.18-μm CMOS process as the front-end of a 14 bit,250 MS/s pipeline ADC.For30 MHz input,the measured SFDR/SNDR of the ADC is 94.7 dB/68.5dB,which can remain over 84.3 dB/65.4dB for input frequency up to 400 MHz.The ADC presents excellent dynamic performance at high input frequency,which is mainly attributed to the parasitics optimized S/H circuit.展开更多
文摘为提高无人机避障的灵活性和可靠性,提出了一种基于LGMD(Lobula Giant Movement Detector)的无人机避障方法,通过将视场分割为上、下、左、右4个方位,形成4个方位竞争的LGMD(C-LGMD),并利用Matlab软件进行算法实现和视频仿真分析,最后将算法移植到无人机硬件系统,开展悬停测试和实时飞行实验研究。由视频仿真分析和悬停测试结果表明,该算法能有效分辨来自不同方位的障碍物,具有较好的避障性能和鲁棒性;在实时飞行测试中,无人机在室内环境中可实现三维空间有效避障,验证了该算法的可靠性。研究结果为进一步探索无人机高效、可靠避障提供参考依据。
基金supported by the Shenzhen Project(No.JSGG20150512162029307)
文摘An IF-sampling S/H is presented,which adopts a flip-around structure,bottom-plate sampling technique and improved input bootstrapped switches.To achieve high sampling linearity over a wide input frequency range,the floating well technique is utilized to optimize the input switches.Besides,techniques of transistor load linearization and layout improvement are proposed to further reduce and linearize the parasitic capacitance.The S/H circuit has been fabricated in 0.18-μm CMOS process as the front-end of a 14 bit,250 MS/s pipeline ADC.For30 MHz input,the measured SFDR/SNDR of the ADC is 94.7 dB/68.5dB,which can remain over 84.3 dB/65.4dB for input frequency up to 400 MHz.The ADC presents excellent dynamic performance at high input frequency,which is mainly attributed to the parasitics optimized S/H circuit.
