The decades-old synchronous memory bus interface has restricted many innovations in the memory system, which is facing various challenges （or walls） in the era of multi-core and big data. In this paper, we argue tha...The decades-old synchronous memory bus interface has restricted many innovations in the memory system, which is facing various challenges （or walls） in the era of multi-core and big data. In this paper, we argue that a message- based interface should be adopted to replace the traditional bus-based interface in the memory system. A novel message interface based memory system called MIMS is proposed. The key innovation of MIMS is that processors communicate with the memory system through a universal and flexible message packet interface. Each message packet is allowed to encapsulate multiple memory requests （or commands） and additional semantic information. The memory system is more intelligent and active by equipping with a local buffer scheduler, which is responsible for processing packets, scheduling memory requests, preparing responses, and executing specific commands with the help of semantic information. Under the MIMS framework, many previous innovations on memory architecture as well as new optimization opportunities such as address compression and continuous requests combination can be naturally incorporated. The experimental results on a 16-core cycle-detailed simulation system show that： with accurate granularity message, MIMS can improve system performance by 53.21% and reduce energy delay product （EDP） by 55.90%. Furthermore, it can improve effective bandwidth utilization by 62.42% and reduce memory access latency by 51% on average.展开更多
基金partially supported by the Strategic Priority Research Program of the Chinese Academy of Sciences under GrantNo.XDA06010401the National Basic Research 973 Program of China under Grant No.2011CB302502+1 种基金the National NaturalScience Foundation of China under Grant Nos.60925009,61221062,61331008the Huawei Research Program under Grant No.YBCB2011030
文摘The decades-old synchronous memory bus interface has restricted many innovations in the memory system, which is facing various challenges （or walls） in the era of multi-core and big data. In this paper, we argue that a message- based interface should be adopted to replace the traditional bus-based interface in the memory system. A novel message interface based memory system called MIMS is proposed. The key innovation of MIMS is that processors communicate with the memory system through a universal and flexible message packet interface. Each message packet is allowed to encapsulate multiple memory requests （or commands） and additional semantic information. The memory system is more intelligent and active by equipping with a local buffer scheduler, which is responsible for processing packets, scheduling memory requests, preparing responses, and executing specific commands with the help of semantic information. Under the MIMS framework, many previous innovations on memory architecture as well as new optimization opportunities such as address compression and continuous requests combination can be naturally incorporated. The experimental results on a 16-core cycle-detailed simulation system show that： with accurate granularity message, MIMS can improve system performance by 53.21% and reduce energy delay product （EDP） by 55.90%. Furthermore, it can improve effective bandwidth utilization by 62.42% and reduce memory access latency by 51% on average.
