为了提高FPGA（Field Programmable Gate Array）的布通率并优化电路的连线长度,在模拟退火算法的基础上,该文提出一种新的FPGA布局算法。该算法在不同的温度区间采用不同的评价函数,高温阶段采用半周长法进行快速优化布局,低温阶段在...为了提高FPGA（Field Programmable Gate Array）的布通率并优化电路的连线长度,在模拟退火算法的基础上,该文提出一种新的FPGA布局算法。该算法在不同的温度区间采用不同的评价函数,高温阶段采用半周长法进行快速优化布局,低温阶段在评价函数中加入变量因子并进行适度的回火处理,以此来优化布局。实验表明,该算法提高了布通率,优化了连线长度,与最具代表性的VPR（Versatile Place and Route）布局算法相比布线通道宽度提高了近6%,电路总的连线长度降低了4-23%。展开更多
The effects of radiation on 3 CG110 PNP bipolar junction transistors(BJTs)are characterized using 50-Me V protons,40-Me V Si ions,and 1-Me V electrons.In this paper,electrical characteristics and deep level transient ...The effects of radiation on 3 CG110 PNP bipolar junction transistors(BJTs)are characterized using 50-Me V protons,40-Me V Si ions,and 1-Me V electrons.In this paper,electrical characteristics and deep level transient spectroscopy(DLTS)are utilized to analyze radiation defects induced by ionization and displacement damage.The experimental results show a degradation of the current gain and an increase in the types of radiation defect with increasing fluences of 50-Me V protons.Moreover,by comparing the types of damage caused by different radiation sources,the characteristics of the radiation defects induced by irradiation show that 50-Me V proton irradiation can produce both ionization and displacement defects in the 3 CG110 PNP BJTs,in contrast to 40-Me V Si ions,which mainly generate displacement defects,and 1-Me V electrons,which mainly produce ionization defects.This work provides direct evidence of a synergistic effect between the ionization and displacement defects caused in PNP BJTs by 50-Me V protons.展开更多
An improved linear-time retiming algorithm is proposed to incrementally optimize the clock period, espe cially considering the influence of the in-out degree of the critical combinational elements. Firslly, the critic...An improved linear-time retiming algorithm is proposed to incrementally optimize the clock period, espe cially considering the influence of the in-out degree of the critical combinational elements. Firslly, the critical elements are selected from all the critical combinational elements to retime. Secondly, for the nodes that cannot be performed with such retiming, register sharing is implemented while the path delay is kept unchanged. The incremental algorithm can be applied with the technology mapping to minimize the critical path delay and obtain fewer registers in the re- timed circuit with the near-optimal clock period. Compared with Singh＇s incremental algorithm, experiments show that the proposed algorithm can reduce the flip-flop count by 11% and look-up table （LUT） count by 5% while improv- ing the minimum clock period by 6%. The runtime is also reduced by 9% of the design flow.展开更多
文摘为了使FPGA(field grogrammable gate array)布局系统能够处理含有快速进位链及IP(intellectual proper-ty)核的复杂电路,在模拟退火算法的基础上,提出一种新的FPGA布局算法。该算法对含有快速进位链和不含快速进位链的电模块分别构造和调用不同的评价函数。以此来优化布局系统,实验结果表明,此布局系统与最具代表性的VPR(versatile place and route)布局系统相比增加了处理进位链和IP核功能,提高了布局系统性能。
文摘为了提高FPGA（Field Programmable Gate Array）的布通率并优化电路的连线长度,在模拟退火算法的基础上,该文提出一种新的FPGA布局算法。该算法在不同的温度区间采用不同的评价函数,高温阶段采用半周长法进行快速优化布局,低温阶段在评价函数中加入变量因子并进行适度的回火处理,以此来优化布局。实验表明,该算法提高了布通率,优化了连线长度,与最具代表性的VPR（Versatile Place and Route）布局算法相比布线通道宽度提高了近6%,电路总的连线长度降低了4-23%。
文摘The effects of radiation on 3 CG110 PNP bipolar junction transistors(BJTs)are characterized using 50-Me V protons,40-Me V Si ions,and 1-Me V electrons.In this paper,electrical characteristics and deep level transient spectroscopy(DLTS)are utilized to analyze radiation defects induced by ionization and displacement damage.The experimental results show a degradation of the current gain and an increase in the types of radiation defect with increasing fluences of 50-Me V protons.Moreover,by comparing the types of damage caused by different radiation sources,the characteristics of the radiation defects induced by irradiation show that 50-Me V proton irradiation can produce both ionization and displacement defects in the 3 CG110 PNP BJTs,in contrast to 40-Me V Si ions,which mainly generate displacement defects,and 1-Me V electrons,which mainly produce ionization defects.This work provides direct evidence of a synergistic effect between the ionization and displacement defects caused in PNP BJTs by 50-Me V protons.
基金Supported by Major National Scientific Research Plan (No. 2011CB933202)
文摘An improved linear-time retiming algorithm is proposed to incrementally optimize the clock period, espe cially considering the influence of the in-out degree of the critical combinational elements. Firslly, the critical elements are selected from all the critical combinational elements to retime. Secondly, for the nodes that cannot be performed with such retiming, register sharing is implemented while the path delay is kept unchanged. The incremental algorithm can be applied with the technology mapping to minimize the critical path delay and obtain fewer registers in the re- timed circuit with the near-optimal clock period. Compared with Singh＇s incremental algorithm, experiments show that the proposed algorithm can reduce the flip-flop count by 11% and look-up table （LUT） count by 5% while improv- ing the minimum clock period by 6%. The runtime is also reduced by 9% of the design flow.
