Crystal morphologies and resistivity of polysilicon trap-rich layers of two-generation trap-rich silicon-on-insulator（TR-SOI） substrates are studied. It is found that the resistivity of the trap-rich layer of genera...Crystal morphologies and resistivity of polysilicon trap-rich layers of two-generation trap-rich silicon-on-insulator（TR-SOI） substrates are studied. It is found that the resistivity of the trap-rich layer of generation 2（TR-G2）is higher than that of generation 1（TR-G1）, although the crystal morphologies of the trap rich layers are the same. In addition, the rf performance of two-generation TR-SOI substrates is investigated by coplanar waveguide lines and inductors. The results show that both the rf loss and the second harmonic distortion of TR-G2 are smaller than those of TR-G1. These results can be attributed to the higher resistivity values of both the trap-rich layer and the high-resistivity silicon（HR-Si） substrate of TR-G2. Moreover, the rf performance of the TR-SOI substrate with thicker buried oxide is slightly better. The second harmonics of various TR-SOI substrates are simulated and evaluated with the harmonic quality factor model as well. It can be predicted that the TR-SOI substrate will see further improvement in rf performance if the resistivities of both the trap-rich layer and HR-Si substrate increase.展开更多
High-resistivity silicon-on-insulator （HR-SOI） and trap-rich high-resistivity silicon-on-insulator （TR-S01） sub- strates have been widely adopted for high-performance rf integrated circuits. Radio-frequency loss a...High-resistivity silicon-on-insulator （HR-SOI） and trap-rich high-resistivity silicon-on-insulator （TR-S01） sub- strates have been widely adopted for high-performance rf integrated circuits. Radio-frequency loss and non- linearity characteristics are measured from coplanar waveguide （CPW） t lines fabricated on HR-SOI and TR-SOI substrates. The patterned insulator structure is introduced to reduce loss and non-linearity char- acteristics. A metal-oxide-semiconductor （MOS） CPW circuit model is established to expound the mechanism of reducing the parasitic surface conductance （PSC） effect by combining the semiconductor characteristic anal- ysis （pseudo-MOS and C-V test）. The rf performance of the CPW transmission lines under dc bias supply is also compared. The TR-SOI substrate with the patterned oxide structure sample has the minimum rf loss （〈0.2 dB/mm up to 10 GHz）, the best non-linearity performance, and reductions of 4 dB and 10 dB are compared with the state-of-the-art TR-SOI sample＇s, HD2 and HD3, respectively. It shows the potential application for integrating the two schemes to further suppress the PSC effect.展开更多
基金Supported by the National Natural Science Foundation of China under Grant Nos 61376021 and 61674159the Program of Shanghai Academic/Technology Research Leader under Grant No 17XD1424500
文摘Crystal morphologies and resistivity of polysilicon trap-rich layers of two-generation trap-rich silicon-on-insulator（TR-SOI） substrates are studied. It is found that the resistivity of the trap-rich layer of generation 2（TR-G2）is higher than that of generation 1（TR-G1）, although the crystal morphologies of the trap rich layers are the same. In addition, the rf performance of two-generation TR-SOI substrates is investigated by coplanar waveguide lines and inductors. The results show that both the rf loss and the second harmonic distortion of TR-G2 are smaller than those of TR-G1. These results can be attributed to the higher resistivity values of both the trap-rich layer and the high-resistivity silicon（HR-Si） substrate of TR-G2. Moreover, the rf performance of the TR-SOI substrate with thicker buried oxide is slightly better. The second harmonics of various TR-SOI substrates are simulated and evaluated with the harmonic quality factor model as well. It can be predicted that the TR-SOI substrate will see further improvement in rf performance if the resistivities of both the trap-rich layer and HR-Si substrate increase.
文摘High-resistivity silicon-on-insulator （HR-SOI） and trap-rich high-resistivity silicon-on-insulator （TR-S01） sub- strates have been widely adopted for high-performance rf integrated circuits. Radio-frequency loss and non- linearity characteristics are measured from coplanar waveguide （CPW） t lines fabricated on HR-SOI and TR-SOI substrates. The patterned insulator structure is introduced to reduce loss and non-linearity char- acteristics. A metal-oxide-semiconductor （MOS） CPW circuit model is established to expound the mechanism of reducing the parasitic surface conductance （PSC） effect by combining the semiconductor characteristic anal- ysis （pseudo-MOS and C-V test）. The rf performance of the CPW transmission lines under dc bias supply is also compared. The TR-SOI substrate with the patterned oxide structure sample has the minimum rf loss （〈0.2 dB/mm up to 10 GHz）, the best non-linearity performance, and reductions of 4 dB and 10 dB are compared with the state-of-the-art TR-SOI sample＇s, HD2 and HD3, respectively. It shows the potential application for integrating the two schemes to further suppress the PSC effect.
