Si-rich silicon nitride films are prepared by plasma-enhanced chemical vapor deposition method, followed by thermal annealing to form the Si nanocrystals（Si-NCs） embedded in Si Nx floating gate MOS structures. The c...Si-rich silicon nitride films are prepared by plasma-enhanced chemical vapor deposition method, followed by thermal annealing to form the Si nanocrystals（Si-NCs） embedded in Si Nx floating gate MOS structures. The capacitance–voltage（C–V）, current–voltage（I–V）, and admittance–voltage（G–V） measurements are used to investigate the charging characteristics. It is found that the maximum flat band voltage shift（△VFB） due to full charged holes（～ 6.2 V） is much larger than that due to full charged electrons（～ 1 V）. The charging displacement current peaks of electrons and holes can be also observed by the I–V measurements, respectively. From the G–V measurements we find that the hole injection is influenced by the oxide hole traps which are located near the Si O2/Si-substrate interface. Combining the results of C–V and G–V measurements, we find that the hole charging of the Si-NCs occurs via a two-step tunneling mechanism. The evolution of G–V peak originated from oxide traps exhibits the process of hole injection into these defects and transferring to the Si-NCs.展开更多
Nanowire devices with back gate are fabricated in a heavy doped ultra thin SOI layer by electron beam lithography. Regular and periodic Coulomb oscillations with single dot behavior are observed in an appropriate back...Nanowire devices with back gate are fabricated in a heavy doped ultra thin SOI layer by electron beam lithography. Regular and periodic Coulomb oscillations with single dot behavior are observed in an appropriate back gate voltage range. The oscillation period can be determined by the back gate capacitance. The role of the back gate can control the electrical characteristics from the multi-dot junction regimes to the single dot junction regimes. These Coulomb oscillations due to single-electron tunneling are not smeared out by thermal vibration energy when the temperature is less than 40 K.展开更多
Room-temperature negative differential resistance(NDR)characteristics are observed in a nanocrystalline Si quantum dot(nc-Si QD)floating-gate MOS structure,which is fabricated by plasma-enhanced chemical vapor deposit...Room-temperature negative differential resistance(NDR)characteristics are observed in a nanocrystalline Si quantum dot(nc-Si QD)floating-gate MOS structure,which is fabricated by plasma-enhanced chemical vapor deposition.Clear multi-NDR peaks for the electrons and holes,shown in the I–V curves,which are significant for the application of multiple value memory and logic,are proved to be induced by electron and hole resonant tunneling into the nc-Si QDs from the substrate.The calculation results indicate that these NDR characteristics should be associated with the Coulomb blockade effect and the quantum confinement effect of the nc-Si QDs.Furthermore,low-temperature I–V characteristics are also investigated to confirm the room-temperature results.展开更多
A nonvolatile memory device with nitrided Si nanocrystals embedded in a floating gate was fabricated. The uniform Si nanocrystals with high density （3× 10^11 cm^-2 ） were deposited on ultra-thin tunnel oxide la...A nonvolatile memory device with nitrided Si nanocrystals embedded in a floating gate was fabricated. The uniform Si nanocrystals with high density （3× 10^11 cm^-2 ） were deposited on ultra-thin tunnel oxide layer （- 3 nm） and followed by a nitridation treatment in ammonia to form a thin silicon nitride layer on the surface of nanocrystals. A memory window of 2.4 V was obtained and it would be larger than 1.3 V after ten years from the extrapolated retention data. The results can be explained by the nitrogen passivation of the surface traps of Si nanoerystals, which slows the charge loss rate.展开更多
The nanocrystal-Si quantum dot （nc-Si QD） floating gate MOS structure is fabricated by using plasma-enhanced chemical vapour deposition （PECVD） and furnace oxidation technology. The capacitance hysteresis in capac...The nanocrystal-Si quantum dot （nc-Si QD） floating gate MOS structure is fabricated by using plasma-enhanced chemical vapour deposition （PECVD） and furnace oxidation technology. The capacitance hysteresis in capacitancevoltage （C - V） measurements confirm the charging effect of nc-Si QDs. Asymmetric charging current peaks both for electrons and holes have been observed in current-voltage （I - V） measurements at room temperature for the first time. The characteristic and the origin of these current peaks in this nc-Si QD MOS structure is in- vestigated systematically. Moreover, the charge density （10^-7 C/cm^2） calculated from the charging current peaks in the I - V measurements at different sweep rates shows that each quantum dot is charged by one carrier. The difference of charging threshold voltages between the electrons and holes charging peaks, △VG, can be explained by the quantum confinement effect of the nc-Si dots in size of about 3.5 nm.展开更多
基金Project supported by the National Basic Research Program of China(Grant No.2010CB934402)the National Natural Science Foundation of China(Grant No.11374153)
文摘Si-rich silicon nitride films are prepared by plasma-enhanced chemical vapor deposition method, followed by thermal annealing to form the Si nanocrystals（Si-NCs） embedded in Si Nx floating gate MOS structures. The capacitance–voltage（C–V）, current–voltage（I–V）, and admittance–voltage（G–V） measurements are used to investigate the charging characteristics. It is found that the maximum flat band voltage shift（△VFB） due to full charged holes（～ 6.2 V） is much larger than that due to full charged electrons（～ 1 V）. The charging displacement current peaks of electrons and holes can be also observed by the I–V measurements, respectively. From the G–V measurements we find that the hole injection is influenced by the oxide hole traps which are located near the Si O2/Si-substrate interface. Combining the results of C–V and G–V measurements, we find that the hole charging of the Si-NCs occurs via a two-step tunneling mechanism. The evolution of G–V peak originated from oxide traps exhibits the process of hole injection into these defects and transferring to the Si-NCs.
基金Supported by the National Basic Research Program of China under Grant No 2006CB932202, and the National Natural Science Foundation of China under Grant Nos 60721063 and 10974091.
文摘Nanowire devices with back gate are fabricated in a heavy doped ultra thin SOI layer by electron beam lithography. Regular and periodic Coulomb oscillations with single dot behavior are observed in an appropriate back gate voltage range. The oscillation period can be determined by the back gate capacitance. The role of the back gate can control the electrical characteristics from the multi-dot junction regimes to the single dot junction regimes. These Coulomb oscillations due to single-electron tunneling are not smeared out by thermal vibration energy when the temperature is less than 40 K.
基金Supported by the National Basic Research Program of China under Grant No 2010CB934402.
文摘Room-temperature negative differential resistance(NDR)characteristics are observed in a nanocrystalline Si quantum dot(nc-Si QD)floating-gate MOS structure,which is fabricated by plasma-enhanced chemical vapor deposition.Clear multi-NDR peaks for the electrons and holes,shown in the I–V curves,which are significant for the application of multiple value memory and logic,are proved to be induced by electron and hole resonant tunneling into the nc-Si QDs from the substrate.The calculation results indicate that these NDR characteristics should be associated with the Coulomb blockade effect and the quantum confinement effect of the nc-Si QDs.Furthermore,low-temperature I–V characteristics are also investigated to confirm the room-temperature results.
基金Supported by the National Basic Research Program of China under Grant No 2006CB932202, and the National Natural Science Foundation of China under Grant Nos 60721063 and 10974091.
文摘A nonvolatile memory device with nitrided Si nanocrystals embedded in a floating gate was fabricated. The uniform Si nanocrystals with high density （3× 10^11 cm^-2 ） were deposited on ultra-thin tunnel oxide layer （- 3 nm） and followed by a nitridation treatment in ammonia to form a thin silicon nitride layer on the surface of nanocrystals. A memory window of 2.4 V was obtained and it would be larger than 1.3 V after ten years from the extrapolated retention data. The results can be explained by the nitrogen passivation of the surface traps of Si nanoerystals, which slows the charge loss rate.
基金Supported by the National Basic Research Programme of China under Grant No 2006CB932202, and the National Natural Science Foundation of China under Grant Nos 60571008 and 60721063.
文摘The nanocrystal-Si quantum dot （nc-Si QD） floating gate MOS structure is fabricated by using plasma-enhanced chemical vapour deposition （PECVD） and furnace oxidation technology. The capacitance hysteresis in capacitancevoltage （C - V） measurements confirm the charging effect of nc-Si QDs. Asymmetric charging current peaks both for electrons and holes have been observed in current-voltage （I - V） measurements at room temperature for the first time. The characteristic and the origin of these current peaks in this nc-Si QD MOS structure is in- vestigated systematically. Moreover, the charge density （10^-7 C/cm^2） calculated from the charging current peaks in the I - V measurements at different sweep rates shows that each quantum dot is charged by one carrier. The difference of charging threshold voltages between the electrons and holes charging peaks, △VG, can be explained by the quantum confinement effect of the nc-Si dots in size of about 3.5 nm.
