A differential complementary LC voltage controlled oscillator （VCO） with high Q on-chip inductor is presented. The parallel resonator of the VCO consists of inversion-mode MOS （I-MOS） capacitors and an on-chip ind...A differential complementary LC voltage controlled oscillator （VCO） with high Q on-chip inductor is presented. The parallel resonator of the VCO consists of inversion-mode MOS （I-MOS） capacitors and an on-chip inductor. The resonator Q factor is mainly limited by the on-chip inductor. It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz. The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process, and the chip area is 1.0 ×0.8 mm2. The free-running frequency is from 5.73 to 6.35 GHz. When oscillating at 6,35 GHz, the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz. The figure of merit of the proposed VCO is -192.13 dBc/Hz.展开更多
A phase-locked loop（PLL） frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator（VCO） is presented.The phase-switching prescaler with a novel modulus control mech...A phase-locked loop（PLL） frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator（VCO） is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm^2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.展开更多
A two-stage differential linear power amplifier （PA） fabricated by 0.18 μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and ...A two-stage differential linear power amplifier （PA） fabricated by 0.18 μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency （PAE） is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 × 0.55 mm2. System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader.展开更多
基金Project supported by the Important National Science and Technology Specific Projects of China(No.2009ZX01031-003-002)the National High Technology Research and Development Program of China(No.2009AA011605)
文摘A differential complementary LC voltage controlled oscillator （VCO） with high Q on-chip inductor is presented. The parallel resonator of the VCO consists of inversion-mode MOS （I-MOS） capacitors and an on-chip inductor. The resonator Q factor is mainly limited by the on-chip inductor. It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz. The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process, and the chip area is 1.0 ×0.8 mm2. The free-running frequency is from 5.73 to 6.35 GHz. When oscillating at 6,35 GHz, the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz. The figure of merit of the proposed VCO is -192.13 dBc/Hz.
基金Project supported by the Important National Science & Technology Specific Projects of China(Nos.2009ZX01031-003-002, 2010ZX03001-004)the National High Technology Research & Development Program of China(No.2009AA011605)
文摘A phase-locked loop（PLL） frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator（VCO） is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm^2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.
基金Project supported by the Ministry of Science & Technology of China(No.2008BAI55B07)
文摘A two-stage differential linear power amplifier （PA） fabricated by 0.18 μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency （PAE） is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 × 0.55 mm2. System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader.
