针对固定频率峰值电流模式PWM升压型DC-DC变换器,给出了一种结构简单、易于集成的电流环路补偿电路的设计方法。该电路的斜坡产生电路可对片内振荡器充放电电容上的电压作V/I转换,其所得到的斜坡电流具有稳定、斜率易于调节等特点;而电...针对固定频率峰值电流模式PWM升压型DC-DC变换器,给出了一种结构简单、易于集成的电流环路补偿电路的设计方法。该电路的斜坡产生电路可对片内振荡器充放电电容上的电压作V/I转换,其所得到的斜坡电流具有稳定、斜率易于调节等特点;而电流采样电路主体采用SENSEFET结合优化的缓冲级和V/I转换电路,从而在提高采样精度的同时,还减小了损耗。整个电路可采用0.6μm 15 V BCD工艺实现。通过Cadence Spectre进行的仿真结果表明,该电路可有效地抑制亚谐波振荡,采样精度达到77.9%,补偿斜率精度达到81.5%。展开更多
A 3 A sink/source G_m-driven CMOS low-dropout regulator（LDO）,specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m（transconductance）driving technique...A 3 A sink/source G_m-driven CMOS low-dropout regulator（LDO）,specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m（transconductance）driving technique,which provides high stability as well as a fast load transient response.The proposed LDO was fabricated by a 0.5μm standard CMOS process,and the die size is as small as 1.0 mm^2.The proposed LDO dissipates 220μA of quiescent current in no-load conditions and is able to deliver up to 3 A of load current.The measured results show that the output voltage can be resumed within 2μs with a less than 1mV overshoot and undershoot in the output current step from-1.8 to 1.8 A with a 0.1μs rising and falling time at three 10μF ceramic capacitors.展开更多
文摘针对固定频率峰值电流模式PWM升压型DC-DC变换器,给出了一种结构简单、易于集成的电流环路补偿电路的设计方法。该电路的斜坡产生电路可对片内振荡器充放电电容上的电压作V/I转换,其所得到的斜坡电流具有稳定、斜率易于调节等特点;而电流采样电路主体采用SENSEFET结合优化的缓冲级和V/I转换电路,从而在提高采样精度的同时,还减小了损耗。整个电路可采用0.6μm 15 V BCD工艺实现。通过Cadence Spectre进行的仿真结果表明,该电路可有效地抑制亚谐波振荡,采样精度达到77.9%,补偿斜率精度达到81.5%。
基金Project supported by the National Natural Science Foundation of China(No60876023)
文摘A 3 A sink/source G_m-driven CMOS low-dropout regulator（LDO）,specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m（transconductance）driving technique,which provides high stability as well as a fast load transient response.The proposed LDO was fabricated by a 0.5μm standard CMOS process,and the die size is as small as 1.0 mm^2.The proposed LDO dissipates 220μA of quiescent current in no-load conditions and is able to deliver up to 3 A of load current.The measured results show that the output voltage can be resumed within 2μs with a less than 1mV overshoot and undershoot in the output current step from-1.8 to 1.8 A with a 0.1μs rising and falling time at three 10μF ceramic capacitors.
