A CMOS low-noise amplifier （LNA） operating at 31.7 GHz with a low input return loss （S11） and high linearity is proposed. The wideband input matching was achieved by employing a simple LC compounded network to gen...A CMOS low-noise amplifier （LNA） operating at 31.7 GHz with a low input return loss （S11） and high linearity is proposed. The wideband input matching was achieved by employing a simple LC compounded network to generate more than one S11 dip below -10 dB level. The principle of the matching circuit is analyzed and the critical factors with significant effect on the input impedance （Zin） are determined. The relationship between the input impedance and the load configuration is explored in depth, which is seldom concentrated upon previously. In addition, the noise of the input stage is modeled using a cascading matrix instead of conventional noise theory. In this way Zin and the noise figure can be calculated using one uniform formula. The linearity analysis is also performed in this paper. Finally, an LNA was designed for demonstration purposes. The measurement results show that the proposed LNA achieves a maximum power gain of 9.7 dB and an input return loss of 〈 -10 dB from 29 GHz to an elevated frequency limited by the measuring range. The measured input-referred compression point and the third order inter-modulation point are -7.8 and 5.8 dBm, respectively. The LNA is fabricated in a 90-nm RF CMOS process and occupies an area of 755 × 670μm2 including pads. The whole circuit dissipates a DC power of 24 mW from one 1.3-V supply.展开更多
This paper proposes a direct injection-locked frequency divider（ILFD） with a wide locking range in the Ka-band. A complementary cross-coupled architecture is used to enhance the overdriving voltage of the switch tra...This paper proposes a direct injection-locked frequency divider（ILFD） with a wide locking range in the Ka-band. A complementary cross-coupled architecture is used to enhance the overdriving voltage of the switch transistor so that the divider locking range is extended efficiently. New insights into the locking range and output power are proposed. A new method to analyze and optimize the injection sensitivity is presented and a layout technique to reduce the parasitics of the cross-coupled transistors is applied to decrease the frequency shift and the locking range degradation. The circuit is designed in a standard 90-nm CMOS process. The total locking range of the ILFD is 43.8% at 34.5 GHz with an incident power of –3.5 dBm. The divider IC consumes 3.6 mW of power at the supply voltage of 1.2 V. The chip area including the pads is 0.50.5 mm2.展开更多
基金Project supported by the National Basic Research Program of China(No.2010CB327404)the National High Technology Research and Development Program of China(No.2011AA10305)the International Cooperation Projects in Science and Technology,China(No. 2011DFA11310)
文摘A CMOS low-noise amplifier （LNA） operating at 31.7 GHz with a low input return loss （S11） and high linearity is proposed. The wideband input matching was achieved by employing a simple LC compounded network to generate more than one S11 dip below -10 dB level. The principle of the matching circuit is analyzed and the critical factors with significant effect on the input impedance （Zin） are determined. The relationship between the input impedance and the load configuration is explored in depth, which is seldom concentrated upon previously. In addition, the noise of the input stage is modeled using a cascading matrix instead of conventional noise theory. In this way Zin and the noise figure can be calculated using one uniform formula. The linearity analysis is also performed in this paper. Finally, an LNA was designed for demonstration purposes. The measurement results show that the proposed LNA achieves a maximum power gain of 9.7 dB and an input return loss of 〈 -10 dB from 29 GHz to an elevated frequency limited by the measuring range. The measured input-referred compression point and the third order inter-modulation point are -7.8 and 5.8 dBm, respectively. The LNA is fabricated in a 90-nm RF CMOS process and occupies an area of 755 × 670μm2 including pads. The whole circuit dissipates a DC power of 24 mW from one 1.3-V supply.
基金Project supported by the National Basic Research Program(No.2010CB327404)the National High Technology Researchand Development Program of China(No.2011AA10305)+1 种基金the International Cooperation Projects in Science and Technology(No.2011DFA11310)the National Natural Science Foundation of China(Nos.60901012,61106024)
文摘This paper proposes a direct injection-locked frequency divider（ILFD） with a wide locking range in the Ka-band. A complementary cross-coupled architecture is used to enhance the overdriving voltage of the switch transistor so that the divider locking range is extended efficiently. New insights into the locking range and output power are proposed. A new method to analyze and optimize the injection sensitivity is presented and a layout technique to reduce the parasitics of the cross-coupled transistors is applied to decrease the frequency shift and the locking range degradation. The circuit is designed in a standard 90-nm CMOS process. The total locking range of the ILFD is 43.8% at 34.5 GHz with an incident power of –3.5 dBm. The divider IC consumes 3.6 mW of power at the supply voltage of 1.2 V. The chip area including the pads is 0.50.5 mm2.
