A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter（ADC） is presented.This ADC with single track-and-hold（T/H） circuits is based on cascaded folding amplifiers and input-connection-improved...A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter（ADC） is presented.This ADC with single track-and-hold（T/H） circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers.The prototype ADC achieves 5.55 bits of the effective number of bits（ENOB） and 47.84 dB of the spurious free dynamic range（SFDR） at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate; it achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30.1-MHz input with a 600-MS/s sampling rate.This ADC has a total power consumption of 25 mW from a 1.4 V supply voltage and occupies 0.17 mm^2 in the 0.13-μm CMOS process.展开更多
A 1,4-V 8-bit 300-MS/s folding and interpolating analog-to-digital converter（ADC） is proposed.Fabricated in the 0.13-μm CMOS process and occupying only 0.6-mm^2 active area,the ADC is especially suitable for embedd...A 1,4-V 8-bit 300-MS/s folding and interpolating analog-to-digital converter（ADC） is proposed.Fabricated in the 0.13-μm CMOS process and occupying only 0.6-mm^2 active area,the ADC is especially suitable for embedded applications.The system is optimized for a low-power purpose.Pipelining sampling switches help to cut down the extra power needed for complete settling.An averaging resistor array is placed between two folding stages for power-saving considerations.The converter achieves 43.4-dB signal-to-noise and distortion ratio and 53.3-dB spurious-free dynamic range at 1-MHz input and 42.1-dB and 49.5-dB for Nyquist input.Measured results show a power dissipation of 34 mW and a figure of merit of 1.14 pJ/convstep at 250-MHz sampling rate at 1.4-V supply.展开更多
基金supported by the National Natural Science Foundation of China(No.90407003)the Science and Technology Commission of Shanghai Municipality(Nos.067062003,08XD14007)the Shanghai-Applied Materials Research and Development Fund(No. 07SA16)
文摘A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter（ADC） is presented.This ADC with single track-and-hold（T/H） circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers.The prototype ADC achieves 5.55 bits of the effective number of bits（ENOB） and 47.84 dB of the spurious free dynamic range（SFDR） at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate; it achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30.1-MHz input with a 600-MS/s sampling rate.This ADC has a total power consumption of 25 mW from a 1.4 V supply voltage and occupies 0.17 mm^2 in the 0.13-μm CMOS process.
基金Project supported by the National Science & Technology Major Projects,China(No.2009ZX03007-002-02)the Program of Shanghai Subject Chief Scientist Fund,China(No.08XD14007).
文摘A 1,4-V 8-bit 300-MS/s folding and interpolating analog-to-digital converter（ADC） is proposed.Fabricated in the 0.13-μm CMOS process and occupying only 0.6-mm^2 active area,the ADC is especially suitable for embedded applications.The system is optimized for a low-power purpose.Pipelining sampling switches help to cut down the extra power needed for complete settling.An averaging resistor array is placed between two folding stages for power-saving considerations.The converter achieves 43.4-dB signal-to-noise and distortion ratio and 53.3-dB spurious-free dynamic range at 1-MHz input and 42.1-dB and 49.5-dB for Nyquist input.Measured results show a power dissipation of 34 mW and a figure of merit of 1.14 pJ/convstep at 250-MHz sampling rate at 1.4-V supply.
